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A Low-Power High-Gain Low Noise Amplifier For Wake-Up Receivers

Title
A Low-Power High-Gain Low Noise Amplifier For Wake-Up Receivers
Translated Title
Wake-Up 수신기들을 위한 저전력, 고 증폭 저 잡음 증폭기 설계
Authors
Kim, Min Woo
DGIST Authors
Kim, Min Woo; Lee, Jung Hyup; Je, Min Kyu
Advisor(s)
Lee, Jung Hyup
Co-Advisor(s)
Je, Min Kyu
Issue Date
2017
Available Date
2017-01-18
Degree Date
2017. 2
Type
Thesis
Keywords
Active balunPseudo-differential LNAQ-enhancementCapacitive cross-couplingBootstrapping capacitoroutput gain-phase balancinginput/output isolationIC변압기Pseudo-차동 저 잡음 증폭기Q강화회로Bootstrapping 커패시터출력 진폭-위상 조절입력/출력 차폐
Abstract
The recent researches are focus on the ultra-low power system like bio-medical device and IoT/IoE devices. In this case, the Wake-Up Receiver (WuRx) is absolutely necessary to make connections between devices with ultra-low power consumption. In the WuRx, the most important block is the Low-Noise Amplifier (LNA). The purpose of LNA in the WuRx is to ensure an accurate communication and reduce overall system power consumption between devices by performing several roles simultaneously on single stage like high gain and low noise and so on. This thesis presents the design of LNA for input stage of WuRx. For low power WuRx architecture, the differential output of tunable high gain, low noise figure, input/output isolation, differential output gain-phase balancing, good linearity, and low power are needed simultaneously. The pseudo-differential LNA incorporates an active single-to-differential conversion. By utilizing Q-enhancement circuit with LC tank at output nodes of pseudo-differential topology, the LNA has a tunable ultra-high gain. And, the both input/output isolation and differential output gain-phase balancing can be achieved by using capacitive cross-coupled technique. We described the bootstrapping capacitor for noise filtering effect in the pseudo-input stage. A 2.4GHz LNA design optimized in a 90nm CMOS process shows that the tolerable differential output gain-phase imbalances are up to 0.08dB and 0.1°, respectively. And, the simulation results show that proposed LNA achieves a noise figure of 4.7 to 5.7dB, and an IIP3 of -26.9dBm to -63.5dBm at the 2.4GHz according to the tunable current of Q-enhancement for obtaining variable gain of 26dB to 56dB with just 90 to 169μA current consumption, and 1V supply voltage. ⓒ 2017 DGIST
Table Of Contents
Ⅰ. Introduction 1 -- Ⅱ. Design of single-to-differential LNA 5 -- 2.1 Impedance matching 5 -- 2.1.1 Basic matching networks for impedance matching 5 -- 2.1.2 Impedance matching using smith chart 9 -- 2.2 LNA topology; Pseudo-differential structure 11 -- 2.3 Size optimization of input transistor in LNA 13 -- 2.4 Q-enhancement technique 15 -- 2.4.1 Understanding of LC tank 15 -- 2.4.2 A negative resistance active circuit for canceling current leakage path 17 -- 2.5 Capacitive cross-coupling technique analysis 19 -- 2.5.1 The size decision of cascode transistor 20 -- 2.5.2 The concept of input/output isolation 23 -- 2.5.2.1 Qualitative interpretation of isolation 24 -- 2.5.2.2 Quantitative interpretation of isolation 25 -- 2.5.3 The intuitive concept of differential gain-phase balancing method 29 -- 2.6 Bootstrapping capacitor 31 -- 2.7 Gain analysis of LNA 35 -- 2.7.1 Gain analysis of pseudo-differential LNA with Q-enhancement 35 -- 2.7.2 Gain analysis of pseudo-differential LNA added CCC 37 -- 2.7.3 Gain analysis of pseudo-differential LNA bootstrapped 41 -- 2.8 Noise figure analysis of LNA 43 -- 2.8.1 The noise of input stage with parasitic capacitances 43 -- 2.8.2 The noise figure analysis of pseudo-differential LNA with Q-enhancement 49 -- 2.8.3 The noise figure analysis of pseudo-differential LNA added CCC 50 -- 2.8.4 The noise figure analysis of pseudo-differential LNA bootstrapped 53 -- 2.9 Output impedance analysis of LNA 54 -- Ⅲ. simulation result of LNA 58 -- 3.1 Size decision of M1 58 -- 3.2 Gain simulation 59 -- 3.3 NF simulation 61 -- 3.4 S11 simulation 63 -- 3.5 Single-to-differential conversion accuracy simulation 65 -- 3.6 Linearity simulation 67 -- 3.7 PVT variation simulation 69 -- 3.8 Consideration of design 72 -- Ⅳ. Conclusion 74
URI
http://dgist.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000002324992
http://hdl.handle.net/20.500.11750/1485
DOI
10.22677/thesis.2324992
Degree
Master
Department
Information and Communication Engineering
University
DGIST
Files:
Collection:
Information and Communication EngineeringThesesMaster


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