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A novel hardware architecture of intra-predictor generator for H.264/AVC Codec

Title
A novel hardware architecture of intra-predictor generator for H.264/AVC Codec
Authors
Kwak, S.[Kwak, Sang Hoon]Kim, J.[Kim, Jin Wook]Har, D.[Har, Dong Soo]
DGIST Authors
Kim, J.[Kim, Jin Wook]
Issue Date
2008
Citation
IEICE Transactions on Information and Systems, E91-D(7), 2083-2086
Type
Article
Article Type
Conference Paper
Keywords
Architectural DesignArchitecture Level OptimizationClock CyclesCore PartDedicated HardwareGate CountH.264/AVCHardwareHardware ImplementationHigh ResolutionIntra PredictorMotion Picture Experts Group StandardsNovel ArchitectureNovel HardwarePixel ValuesReal-Time EncodingVideo Recording
ISSN
0916-8532
Abstract
The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work [3]. Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.
URI
http://hdl.handle.net/20.500.11750/3576
DOI
10.1093/ietisy/e91-d.7.2083
Publisher
Institute of Electronics, Information and Communication Engineers
Files:
There are no files associated with this item.
Collection:
Information and Communication EngineeringInfoLab1. Journal Articles


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