Cited 0 time in
Cited 0 time in
A novel hardware architecture of intra-predictor generator for H.264/AVC Codec
- A novel hardware architecture of intra-predictor generator for H.264/AVC Codec
- Kwak, S.[Kwak, Sang Hoon]; Kim, J.[Kim, Jin Wook]; Har, D.[Har, Dong Soo]
- DGIST Authors
- Kim, J.[Kim, Jin Wook]
- Issue Date
- IEICE Transactions on Information and Systems, E91-D(7), 2083-2086
- Article Type
- Conference Paper
- Architectural Design; Architecture Level Optimization; Clock Cycles; Core Part; Dedicated Hardware; Gate Count; H.264/AVC; Hardware; Hardware Implementation; High Resolution; Intra Predictor; Motion Picture Experts Group Standards; Novel Architecture; Novel Hardware; Pixel Values; Real-Time Encoding; Video Recording
- The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work . Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.
- Institute of Electronics, Information and Communication Engineers
There are no files associated with this item.
- Information and Communication EngineeringInfoLab1. Journal Articles
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.