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A 4.7MHz 53MuW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs
- A 4.7MHz 53MuW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs
- Lee, J.[Lee, Junghyup]; Park, P.[Park, Pyoungwon]; Cho, S.[Cho, SeongHwan]; Je, M.[Je, Minkyu]
- DGIST Authors
- Je, M.[Je, Minkyu]
- Issue Date
- 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers, 58, 106-107
- Article Type
- Conference Paper
- Low-power CMOS reference clock oscillators have been widely used in miniaturized SoCs for emerging microsystems such as implantable biomedical devices and smart sensors [1-3]. In such SoCs, as the supply voltage shrinks and the level of analog and digital circuit integration increases to meet rigorous power and area constraints, the noise from other blocks (especially digital blocks) couples through supply and ground lines and poses a serious threat to the performance of CMOS reference clock oscillators. © 2015 IEEE.
- Institute of Electrical and Electronics Engineers Inc.
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