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Hardware architecture design and implementation for FMCW radar signal processing algorithm

Title
Hardware architecture design and implementation for FMCW radar signal processing algorithm
Authors
Hyun, Eu GinLee, Jong Hun
DGIST Authors
Hyun, Eu GinLee, Jong Hun
Issue Date
2015
Citation
2014 8th Conference on Design and Architectures for Signal and Image Processing, DASIP 2014, 2015-May
Type
Conference
Article Type
Conference Paper
ISBN
9790000000000
ISSN
2164-9766
Abstract
Chirp-sequence-based Frequency Modulation Continuous Wave (FMCW) radar is effective at detecting range and velocity of a target. However, the target detection algorithm is based on two-dimensional Fast Fourier Transform, which uses a great deal of data over several PRIs (Pulse Repetition Intervals). In particular, if the multiple-receive channel is employed to estimate the angle position of a target; even more computational complexity is required. In this paper, we report on how a newly developed signal processing module is implemented in the FPGA, and on its performance measured under test conditions. Moreover, we have presented results from analysis of the use of hardware resources and processing times. © 2014 European Electronic Chips & Systems design Initiative - ECSI.
URI
http://hdl.handle.net/20.500.11750/5488
DOI
10.1109/DASIP.2014.7115643
Publisher
IEEE Computer Society
Related Researcher
Files:
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Collection:
Convergence Research Center for Future Automotive Technology2. Conference Papers


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