https://scholar.dgist.ac.kr/handle/20.500.11750/11853 2026-04-04T11:39:15Z 2026-04-04T11:39:15Z Song, Chong-Myeong Park, Jaewoo Lee, Shinbuhm Kwon, Hyuk-Jun https://scholar.dgist.ac.kr/handle/20.500.11750/60031 2026-02-10T02:40:16Z 2025-11-30T15:00:00Z

Title: Achieving wide-range steep slopes in SnS2 negative capacitance transistors through an isolated band structure and thermionic emission enhancement via Bi contacts Author(s): Song, Chong-Myeong; Park, Jaewoo; Lee, Shinbuhm; Kwon, Hyuk-Jun Abstract: Negative capacitance FETs aim for sub-60 mV dec-1 switching to curb power consumption, but often encounter instability and narrow steep-slope windows. We present a hysteresis-free NCFET that strategically utilizes a 2D SnS2 channel. The inherent isolated conduction band of SnS2, yielding a step-like density of states, is pivotal for sharp turn-on characteristics when effectively coupled with the negative capacitance effect. The SnS2 channel is integrated with an La:HfO2/HfO2 ferroelectric-dielectric gate stack and Bi contacts. This architecture shows an average subthreshold swing of 34 mV dec-1 across four current decades, maintaining sub-60 mV dec-1 operation over this wide range, and enabling sub-0.4 V operation. Bi contact is key, minimizing Fermi-level pinning at the SnS2/metal interface. This expands the thermionic emission region, allowing the negative capacitance to fully leverage the distinct properties of SnS2 for sustained wide-range steep-slope performance. This work demonstrates a novel approach to ultralow-power transistors by integrating an isolated-band semiconductor, optimized ferroelectric, and contact engineering.

2025-11-30T15:00:00Z Kwon, Hyuk-Jun https://scholar.dgist.ac.kr/handle/20.500.11750/59975 2026-02-09T08:40:14Z 2025-11-30T15:00:00Z

Title: Materials Horizons Emerging Investigator Series: Professor Hyuk-Jun Kwon, Daegu Gyeongbuk Institute of Science and Technology (DGIST), Daegu, Republic of Korea Author(s): Kwon, Hyuk-Jun Abstract: Our Emerging Investigator Series features exceptional work by early-career researchers working in the field of materials science.

2025-11-30T15:00:00Z Lee, Junhee Yoon, Dongjo Lee, Jungha Kim, Duhee Kim, Eunui Yoon, Jong-Hyeok Kwon, Hyuk-Jun Chung, Seungjun Nam, Yoonkey Kang, Hongki https://scholar.dgist.ac.kr/handle/20.500.11750/59973 2026-03-03T01:10:13Z 2026-01-31T15:00:00Z

Title: High-Spatiotemporal-Resolution Transparent Thermoelectric Temperature Sensor Arrays Reveal Temperature-Dependent Windows for Reversible Photothermal Neuromodulation Author(s): Lee, Junhee; Yoon, Dongjo; Lee, Jungha; Kim, Duhee; Kim, Eunui; Yoon, Jong-Hyeok; Kwon, Hyuk-Jun; Chung, Seungjun; Nam, Yoonkey; Kang, Hongki Abstract: Photothermal neural stimulation enables optical excitation or inhibition of neural activity depending on the dynamics of localized temperature changes, offering high spatial resolution without genetic modification. However, quantitative analysis of these temperature dynamics remains limited due to the lack of suitable direct sensing technologies, posing a challenge to the safe and controlled application of photothermal neural stimulation techniques. This challenge is addressed by developing transparent thermoelectric temperature sensor arrays with high spatiotemporal resolution, integrated with electrical and optical recording capabilities. These microscale sensors stably and accurately capture rapid temperature increases and decreases, and thermal equilibrium induced by thermo-plasmonic effects at the neural interface, regardless of the environment. The multifunctional platform allows simultaneous electrical and optical monitoring of neural responses during the photothermal stimulation, enabling detailed analysis of the correlation between localized temperature changes and neural activities. a reversible neural inhibition window (1.4-4.5 degrees C) and thresholds for irreversible damage (>6.1 degrees C) are identifyed. Using high temporal-resolution sensing, localized thermo-plasmonic temperature dynamics over tens of milliseconds, and associated neural signal suppression and reactivation are captured. This approach provides unprecedented insight into the interplay between photothermal effects and neural activity, establishing a foundation for precise, temperature-guided neuromodulation therapies and advanced neural circuit research.

2026-01-31T15:00:00Z Sim, Young-Jun Kim, Junil Lee, Jieun Lee, Byeongmoon Jang, Jae Eun Kwon, Hyuk-Jun https://scholar.dgist.ac.kr/handle/20.500.11750/59972 2026-02-09T18:01:14Z 2025-11-30T15:00:00Z

Title: Hole Current Enhancement Using W1-x Cr x Se2 Alloy Interface for p-Type WSe2 FETs Author(s): Sim, Young-Jun; Kim, Junil; Lee, Jieun; Lee, Byeongmoon; Jang, Jae Eun; Kwon, Hyuk-Jun Abstract: Two-dimensional (2D) transition-metal dichalcogenides (TMDs) have emerged as promising candidates for next-generation semiconductor devices. Among TMDs, tungsten diselenide (WSe2) is regarded as an ideal material for p-type field-effect transistors (FETs). However, the realization of high-performance p-type devices remains limited due to undesired ambipolar behavior and high contact resistance. These challenges originate from Fermi level pinning (FLP) caused during conventional deposition processes. Although van der Waals (vdW) contacts have been introduced to overcome FLP, their implementation faces difficulties due to contamination-induced degradation and limitations in CMOS process compatibility. In this study, we demonstrate a scalable approach for p-type contact via the W1-xCrxSe2 alloy interface. It has been reported that Cr incorporation reduces the bandgap of WSe2, while CrxSey exhibits p-type semimetal properties. Leveraging these properties, thermal annealing of Cr contacts enables the formation of WSe2/W1-xCrxSe2/Cr layers at the contact region. This interfacial alloy effectively suppresses FLP, eliminates undesirable ambipolar behavior, and enhances hole injection. The resulting devices achieve a Schottky barrier height as low as 61.1 meV and reduce contact resistance by approximately 3 orders of magnitude. Consequently, W1-xCrxSe2 alloy interface contact WSe2 FETs exhibit robust p-type performance with an average on/off current ratio of 2.19 x 10(8) across 20 devices. These findings present a practical and scalable strategy for engineering low-resistance p-type contacts in WSe2, providing an important step toward the integration of TMD-based complementary logic in future scaled CMOS technologies.

2025-11-30T15:00:00Z