https://scholar.dgist.ac.kr/handle/20.500.11750/16131 2026-04-04T12:10:40Z 2026-04-04T12:10:40Z Kim, Donggeon Gharibdoust, Kiarash Tajalli, Armin Lee, Kyoungtae Kim, Gain https://scholar.dgist.ac.kr/handle/20.500.11750/60118 2026-02-25T08:40:13Z 2025-08-07T15:00:00Z

Title: A Spectral-Efficient Low-Power NRZ/PAM-4 Dual-Mode Wireline Transmitter for Multidrop Interfaces Author(s): Kim, Donggeon; Gharibdoust, Kiarash; Tajalli, Armin; Lee, Kyoungtae; Kim, Gain Abstract: This paper presents a reconfigurable and energy-efficient digital spectrum shaping signaling (DSSS) for multidrop interfaces, where the output spectrum of the transmitted data is shaped using the 2-times repetitive block transmission to avoid frequency notches in the multidrop channel, thereby achieving a data rate up to 4x the first channel notch frequency. In conventional wireline transceivers (TRX), compensating for frequency notches requires a large number of decision feedback equalizer (DFE) taps at the receiver, resulting in significant area and power overhead. In contrast, the proposed DSSS architecture supports spectrum-efficient reconfigurable dual-mode NRZ/PAM4, reducing required equalization efforts and improving energy efficiency. The proposed scheme and its transmitter (TX) were first validated through event-driven behavioral simulations using XMODEL and verified with equipment-based measurements. Post-layout simulation results in 28nm CMOS process demonstrated 4 Gb/s data rate communicating over a channel having its first > 30 dB notch at 1 GHz, with a 235mV vertical eye opening and a TX energy efficiency of 0.39 pJ/b at 0.8V supply.

2025-08-07T15:00:00Z Jang, Seoyoung Lee, Jaewon Kossel, Marcel André Brändli, Matthias Morf, Thomas Francese, Pier Andrea Kim, Gain https://scholar.dgist.ac.kr/handle/20.500.11750/59291 2025-12-30T07:40:10Z 2025-09-08T15:00:00Z

Title: A 144 mW 76 Gb/s DAC-Based Discrete Multitone Wireline Transmitter in 5nm FinFET Author(s): Jang, Seoyoung; Lee, Jaewon; Kossel, Marcel André; Brändli, Matthias; Morf, Thomas; Francese, Pier Andrea; Kim, Gain Abstract: This paper presents a 76 Gb/s digital-to-analog converter (DAC)-based discrete multitone (DMT) wireline transmitter (TX) fabricated in 5 nm FinFET. Bit and power loading with 32/64/128-QAM across 31 orthogonal subchannels is demon-strated over a channel with 9.7 dB insertion loss (IL), achieving a bit error rate (BER) of 2.1 E-4. The prototype consumes 144 mW from 0.675 V digital and 0.725 V analog supplies, resulting in an energy efficiency of 1.89 pJ/b. An on-chip DSP performs subchannel-wise bit/power allocation and spectral shaping using a 64-tap inverse fast Fourier transform (IFFT) and cyclic prefix (CP) insertion. Compared to conventional PAM-based TXs, the proposed architecture provides improved bandwidth efficiency and signal-to-noise ratio (SNR) through frequency-domain modulation and equalization. This work is the first demonstration of a DAC-based DMT TX at 76 Gb/s data rate fabricated in advanced CMOS technology.

2025-09-08T15:00:00Z Kim, Donggeon Kim, Seongjin Kim, Gain https://scholar.dgist.ac.kr/handle/20.500.11750/58412 2026-02-11T15:10:42Z 2025-01-20T15:00:00Z

Title: A Time-Domain Analysis, Modeling and Optimization of Analog Amplitude-Modulated Multi-Tone Serial Data Transceivers Author(s): Kim, Donggeon; Kim, Seongjin; Kim, Gain Abstract: This paper presents a versatile and fast time-domain architectural modeling framework for high-speed serial data transceivers (TRX) that can employ various analog modulation schemes. We highlight a modeling of TRXs employing an analog multi-tone signaling, which is not straightforward to model and hard to optimize with conventional serial link modeling tools. A method to limit the computing system's memory usage when simulating a data transmission of a long bit-stream, e.g., > 10 Mbits, is also described. The reliability of the modeling framework is proven by some comparisons with a highly-trusted commercial tool for a conventional TRX architecture. © 2025 IEEE.

2025-01-20T15:00:00Z Lee, Jaewon Francese, Pier-Andrea Brandli, Matthias Morf, Thomas Kossel, Marcel Jang, Seoyoung Kim, Gain https://scholar.dgist.ac.kr/handle/20.500.11750/58273 2025-08-12T09:10:35Z 2025-02-16T15:00:00Z

Title: A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET Author(s): Lee, Jaewon; Francese, Pier-Andrea; Brandli, Matthias; Morf, Thomas; Kossel, Marcel; Jang, Seoyoung; Kim, Gain Abstract: The growing demand for higher communication bandwidth between processors through wired interconnects in large-scale servers has been driving the need to increase the perlane data rate beyond the current 112Gb/s. Recently demonstrated analog-to-digital converter (ADC)-based receiver (RX) prototypes with >100Gb/s data rate typically employ a parallel feed-forward equalizer (FFE) with a large number of taps, 1-tap decision feedback equalizer (DFE) [1-5], and maximum likelihood sequence estimator (MLSE) as option [6-8]. As the data rate grows exponentially, the pulse response length and the number of corresponding inter-symbol interference (ISI) cursors increase accordingly [5,8]. As the length of the pulse response gets doubled, the FFE tap count also needs to be increased accordingly, which results in substantial area and power overhead. The DFE feedback loop timing closure also gets more stringent as Baudrate increases [9]. With an increased pulse amplitude modulation (PAM) order, the DFE and MLSE design complexity increases exponentially [6-8]. While a >100Gb/s PAM-4 transceiver (TRX) can effectively equalize smooth channels [2-5], ripples and notches in the frequency response of the channel can significantly degrade the equalization performance of the current PAM-4 TRX. © 2025 IEEE.

2025-02-16T15:00:00Z