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  <title>Repository Collection: null</title>
  <link rel="alternate" href="https://scholar.dgist.ac.kr/handle/20.500.11750/47660" />
  <subtitle />
  <id>https://scholar.dgist.ac.kr/handle/20.500.11750/47660</id>
  <updated>2026-04-05T01:26:46Z</updated>
  <dc:date>2026-04-05T01:26:46Z</dc:date>
  <entry>
    <title>A Spectral-Efficient Low-Power NRZ/PAM-4 Dual-Mode Wireline Transmitter for Multidrop Interfaces</title>
    <link rel="alternate" href="https://scholar.dgist.ac.kr/handle/20.500.11750/60118" />
    <author>
      <name>Kim, Donggeon</name>
    </author>
    <author>
      <name>Gharibdoust, Kiarash</name>
    </author>
    <author>
      <name>Tajalli, Armin</name>
    </author>
    <author>
      <name>Lee, Kyoungtae</name>
    </author>
    <author>
      <name>Kim, Gain</name>
    </author>
    <id>https://scholar.dgist.ac.kr/handle/20.500.11750/60118</id>
    <updated>2026-02-25T08:40:13Z</updated>
    <published>2025-08-07T15:00:00Z</published>
    <summary type="text">Title: A Spectral-Efficient Low-Power NRZ/PAM-4 Dual-Mode Wireline Transmitter for Multidrop Interfaces
Author(s): Kim, Donggeon; Gharibdoust, Kiarash; Tajalli, Armin; Lee, Kyoungtae; Kim, Gain
Abstract: This paper presents a reconfigurable and energy-efficient digital spectrum shaping signaling (DSSS) for multidrop interfaces, where the output spectrum of the transmitted data is shaped using the 2-times repetitive block transmission to avoid frequency notches in the multidrop channel, thereby achieving a data rate up to 4x the first channel notch frequency. In conventional wireline transceivers (TRX), compensating for frequency notches requires a large number of decision feedback equalizer (DFE) taps at the receiver, resulting in significant area and power overhead. In contrast, the proposed DSSS architecture supports spectrum-efficient reconfigurable dual-mode NRZ/PAM4, reducing required equalization efforts and improving energy efficiency. The proposed scheme and its transmitter (TX) were first validated through event-driven behavioral simulations using XMODEL and verified with equipment-based measurements. Post-layout simulation results in 28nm CMOS process demonstrated 4 Gb/s data rate communicating over a channel having its first &gt; 30 dB notch at 1 GHz, with a 235mV vertical eye opening and a TX energy efficiency of 0.39 pJ/b at 0.8V supply.</summary>
    <dc:date>2025-08-07T15:00:00Z</dc:date>
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