https://scholar.dgist.ac.kr/handle/20.500.11750/121 2026-11-15T15:11:52Z https://scholar.dgist.ac.kr/handle/20.500.11750/61150 Title: Systematic optimization of low-temperature ALD ZnO thin-film transistors with epoxy interlayer toward monolithic 3D integration Author(s): Park, Heechang; Lee, Jeonghun; Jang, Jeonggyun; Pyo, Goeun; Kwon, Hyuk-Jun; Lee, Byeongmoon; Shin, Jeong Hee; Jang, Jae Eun Abstract: Monolithic three-dimensional (3D) integration of thin-film transistors (TFTs) above silicon platforms is uniquely enabled when every back-end-of-line step can be confined below 200 degrees C, a thermal budget that opens the door to polymer interlayers as stacking spacers, an option foreclosed to higher-temperature oxide-TFT systems. ZnO grown by atomic layer deposition (ALD) is one of the few channel materials compatible with this constraint, yet operating at the sub-200 degrees C limit narrows the process window for each step (channel growth, post-deposition treatment, dielectric-channel interface, and structural interlayer) and how these steps jointly determine stackrelevant device behavior has not been fully resolved. We present a unified optimization study that holds the entire process flow within this sub-200 degrees C envelope while addressing all four steps in a single platform. On the mechanistic side, co-sweeping film thickness (15-55 nm) and air-anneal duration (0-180 min) identified a 30-nm channel annealed for 60 min as the operating point delivering the lowest subthreshold slope (97.8 mV dec(-1)) and the smallest combined bias-stress drift (| Delta V-th| = 1.10 V); O 1 s X-ray photoelectron spectra revealed that the V-O-related oxygen-deficient signal continues to shrink past 60 min while electrical metrics worsen, suggesting that defect balance, rather than defect minimization, better captures the conditions for optimal performance. On the application side, ozone post-treatment of HfO2 suppresses interface frequency dispersion to 2.28 % (vs. 140 % untreated), and an epoxy resin-based polymer interlayer enables top-stack ZnO TFTs that match identically processed reference devices on a Si substrate within Delta V-th approximate to +12 mV. This polymer-based stacking route contrasts with the inorganic interlayers (SiO2, HfO2, Al2O3) more commonly used in prior oxide-TFT stacking studies. These findings collectively outline a coherent, fully sub-200 degrees C pathway toward a polymer-ready monolithic ZnO TFT stack. 2026-12-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/61137 Title: Multifunctional tactile sensor system for tactile recorder Author(s): 장정균; 김동수; Sim, Min Kyung; Kang, Min Soo; Shin, Kwonsik; Lee, Junghyup; Kang, Hongki; Kwon, Hyuk-Jun; Jang, Jae Eun Abstract: Recent advances in robotic systems have enabled ultrafine control and precision comparable to that of human hands. However, structural constraints of robotic hands require tactile sensors with high functional complexity and precision while maintaining a simple design. Analogous to vision sensors, tactile sensors would benefit from the ability to record key tactile parameters, including pressure, temperature, and surface texture. This study presents a multifunctional tactile sensor integrating a piezoelectric pressure sensor and a resistive temperature sensor within a single body, along with a tactile recorder system for real-time data acquisition and analysis. The temperature sensor's electrodes also serve as those of the pressure sensor, achieving structural integration but functional separation. The sensor exhibits a response time of less than 10 ms and sensitivities of 0.69 mV/kPa and 2.7 Omega/degrees C for pressure and temperature, respectively. A deviation of 4.68 mV across 25 sensing cells demonstrates excellent uniformity, enabling high-resolution surface mapping and 3D topography rendering. An experimentally derived compensation formula minimizes pyroelectric-induced errors, ensuring accurate pressure readout under varying temperatures. The tactile recorder visualizes and stores signals for subsequent analysis of surface texture and temperature-dependent tactile responses. This work demonstrates a structurally simple yet functionally rich platform for tactile sensing and recording in artificial tactile interfaces. 2026-10-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/61071 Title: Simultaneous Enhancement of Performance and Stability in Dual-Gate a-IGZO Thin-Film Transistors via Single-Step Laser Annealing for Capacitor-Less DRAM Author(s): 권시현; Kim, Junil; Park, Geuntae; Kim, Minseok; Hwang, Woohyun; Kim, Wanki; Ha, Daewon; Lee, Byeongmoon; Jang, Jae Eun; Kwon, Hyuk-Jun Abstract: Wide-bandgap amorphous oxide semiconductors (AOSs), particularly indium-gallium-zinc-oxide (IGZO), offer ultralow off-current and back-end-of-line compatibility, making them attractive for advanced dynamic random access memory (DRAM). In capacitor-less two-transistor (2T0C) DRAM, dual-gate (DG) a-IGZO TFTs are promising read transistors, but achieving a stable positive threshold voltage (V-th) typically reduces field-effect mobility (& micro;(FE)) and increases contact resistance (R-C), limiting fast operation. This study introduces a spatially selective laser annealing strategy that overcomes this limitation in a single step. The steep thermal gradient promotes oxygen incorporation at the top-gate dielectric/channel interface, passivating defects without severely depleting carrier density. Simultaneously, WOx interlayer removal combined with oxygen redistribution forms conductive n(+) regions at source/drain contacts. This dual modification stabilizes the channel and reduces R-C, enabling both high & micro;(FE) (37.9 cm(2) V-1 s(-1)) and a stable positive V-th (0.27 V). The optimized devices exhibit small Delta V-th under bias stress and reliable operation, demonstrating the read function of 2T0C DRAM, maintaining stable "0/1" state discrimination and wide memory windows (>10(5)) for over 10 000 s. This single-step process provides a practical route to overcome the performance-stability trade-off in AOS TFTs, highlighting strong potential for emerging memory applications. 2026-09-30T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/60546 Title: Inkjet-Printed BaTiO3 Nanoparticle-Embedded Capacitor Array for Physical Unclonable Function Author(s): Hong, Woongki; Bissannagari, Murali; Cho, Youngjae; Jang, Jae Eun; Kwon, Hyuk-Jun; Kang, Hongki Abstract: Nanoparticle (NP)-based physical unclonable functions (PUFs) have attracted attention as a digital fingerprint technology that alternates with microfabrication-based PUFs by utilizing natural randomness at the nanoscale. Mostly NP-based optical PUFs have been proposed due to the absence of nanomaterial fabrication method compatible with microelectronics, but the need for a bulky optical readout system makes it difficult to utilize them in microelectronics. In this work, we developed the NP-based capacitor PUF (CAP-PUF) technology that can be read electrically and integrated into microelectronics while utilizing the benefit of the natural physical randomness of NPs. We incorporated a high-k BaTiO3 NP inkjet printing micropatterning process for the fabrication of the NP-embedded CAP-PUF array. The inkjet-printing parameters have been optimized to maximize the natural randomness of the BaTiO3 NP micropatterns by increasing the intrinsic stochasticity, especially the fluid dynamics that occurring during the multilayer printing. The BaTiO3 NP-embedded CAP-PUF array shows high security performance, showing the inter-hamming distance of 0.52, uniformity of 0.44, entropy of 0.989, and intra-hamming distance up to 0.064. High-k NP inkjet-printing-based CAP-PUFs can provide highly unique digital fingerprints based on the intrinsic randomness in nanoscale for microelectronics. 2026-05-31T15:00:00Z