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    <title>Repository Collection: null</title>
    <link>https://scholar.dgist.ac.kr/handle/20.500.11750/123</link>
    <description />
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        <rdf:li rdf:resource="https://scholar.dgist.ac.kr/handle/20.500.11750/60336" />
        <rdf:li rdf:resource="https://scholar.dgist.ac.kr/handle/20.500.11750/59195" />
        <rdf:li rdf:resource="https://scholar.dgist.ac.kr/handle/20.500.11750/59160" />
        <rdf:li rdf:resource="https://scholar.dgist.ac.kr/handle/20.500.11750/58777" />
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    <dc:date>2026-06-03T21:49:53Z</dc:date>
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  <item rdf:about="https://scholar.dgist.ac.kr/handle/20.500.11750/60336">
    <title>고차 노이즈-쉐이핑 특성을 갖는 SAR 아날로그-디지털 변환 장치</title>
    <link>https://scholar.dgist.ac.kr/handle/20.500.11750/60336</link>
    <description>Title: 고차 노이즈-쉐이핑 특성을 갖는 SAR 아날로그-디지털 변환 장치
Author(s): 이정협; 장재은; 김근하</description>
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  <item rdf:about="https://scholar.dgist.ac.kr/handle/20.500.11750/59195">
    <title>ELECTRICAL STIMULATION DEVICE HAVING WIDE RANGE OF OPERATING VOLTAGE</title>
    <link>https://scholar.dgist.ac.kr/handle/20.500.11750/59195</link>
    <description>Title: ELECTRICAL STIMULATION DEVICE HAVING WIDE RANGE OF OPERATING VOLTAGE
Author(s): 신연재; 이정협; 강홍기; 위정윤; 장재은
Abstract: Disclosed is an electrical stimulation circuit having a wide range of operating voltage while exhibiting excellent power efficiency. The disclosed electrical stimulation circuit includes a bias circuit comprising an NMOS transistor or a PMOS transistor. The bias circuit enables the transistors to operate at a stable voltage even when the operating voltage varies above or below a threshold value. The electrical stimulation circuit has a wide range of operating voltage while exhibiting excellent power efficiency, and occupies a small area, thereby being advantageous for miniaturization.</description>
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  <item rdf:about="https://scholar.dgist.ac.kr/handle/20.500.11750/59160">
    <title>수직 박막 트랜지스터 및 이의 제조 방법</title>
    <link>https://scholar.dgist.ac.kr/handle/20.500.11750/59160</link>
    <description>Title: 수직 박막 트랜지스터 및 이의 제조 방법
Author(s): 유민지; 장재은; 최원혁; 표고은; 박동혁; 박희창; 이정훈
Abstract: 본 발명의 다양한 실시예에 따른 수직 박막 트랜지스터는, 게이트 전극; 상기 게이트 전극 상에 배치되는 제1 절연층; 상기 제1 절연층 상에 배치되고 홀을 포함하는 제1 전극; 상기 제1 전극 상에 배치되는 채널층; 및 상기 채널층 상에 배치되는 제2 전극을 포함하고, 상기 제1 전극 및 상기 제2 전극 사이에 홀을 포함하는 제2 절연층을 포함할 수 있다. 본 발명의 다양한 실시예에 따른 수직 박막 트랜지스터의 제조 방법은, 내장 마스크를 포함하는 기판을 준비하는 단계; 상기 기판 상에 홀을 포함하는 제1 전극을 형성하는 단계; 및 상기 기판 상에 홀을 포함하는 제2 절연층을 형성하는 단계를 포함할 수 있다.</description>
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  <item rdf:about="https://scholar.dgist.ac.kr/handle/20.500.11750/58777">
    <title>Vacuum tunneling device and method of manufacturing same</title>
    <link>https://scholar.dgist.ac.kr/handle/20.500.11750/58777</link>
    <description>Title: Vacuum tunneling device and method of manufacturing same
Author(s): 김소희; 허수진; 장현우; 최기순; 장재은
Abstract: The invention provides a vacuum tunneling device and a method for manufacturing the same. The method comprises the following steps: forming a tunneling device on a substrate; forming an insulating interlayer on the substrate, wherein the insulating interlayer is provided with an opening for exposing the tunneling device; and performing a tilted deposition process in the vacuum chamber to form a sealing layer on the insulating interlayer such that the sealing layer fills an upper portion of the opening.</description>
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