https://scholar.dgist.ac.kr/handle/20.500.11750/16129 2026-08-23T23:10:02Z https://scholar.dgist.ac.kr/handle/20.500.11750/60622 Title: A 76-Gb/s DSP-DAC-Based Discrete Multitone Wireline Transmitter in 5-nm FinFET Author(s): Jang, Seoyoung; Kossel, Marcel; Lee, Jaewon; Brandli, Matthias; Morf, Thomas; Choi, Yujin; Kim, Donggeon; Kang, Gayoung; Choi, Yoonji; Francese, Pier-Andrea; Kim, Gain Abstract: This article presents a 76-Gb/s digital-to-analog converter (DAC)-based discrete multitone (DMT) wireline transmitter (TX) fabricated in 5-nm FinFET. The TX employs a 16-way parallel multi-path delay feedback (MDF) inverse fast Fourier transform (IFFT) processor for area-efficient implementation. The TX digital signal processor (DSP) includes on-chip bit/power-loading and cyclic-prefix (CP) insertion logic and supports 4- to 256-QAM modulation formats across 31 orthogonal subchannels. The time-domain DMT samples generated by the TX DSP are converted into analog waveform using a source-series termination (SST)-based DAC. The prototype is demonstrated over a channel with 9.7-dB insertion loss (IL) at Nyquist, achieving a bit error rate (BER) of 2.1E-4 with a total power consumption of 144 mW from 0.735-V digital and 0.725-V analog supplies, resulting in an energy efficiency of 1.89 pJ/b. The proposed DMT TX improves bandwidth efficiency and signal-to-noise ratio (SNR) over conventional pulse-amplitude modulation (PAM)-based transmitters by employing frequency-domain modulation and equalization. This work is the first demonstration of a DAC-based DMT TX operating at >76 Gb/s fabricated in advanced CMOS technology. 2026-06-30T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/60476 Title: Fixed-Point Implementation Analysis of MLSE Receiver DSP for High-Speed Wireline Transceivers Author(s): Kwon, Dohyeon; Kim, Donggeon; Choi, Yujin; Leblebici, Yusuf; Kim, Gain Abstract: This paper analyzes the fixed-point (FXP) implementation of the maximum-likelihood sequence estimation (MLSE) engine for high-speed PAM-4 wireline transceivers (TRXs). Quantization effects in the ADC/FFE output, branchmetric (BM), and path-metric (PM) computations are systematically evaluated through end-to-end BER simulations at 118Gb/s over a 28.5dB-loss channel. Comprehensive precision sweeps show that insufficient quantization at early DSP stages, particularly in the FFE output and BM computation, causes irreversible BER degradation even when later stages maintain high precision. The analysis identifies the dominant precision bottlenecks and provides quantitative design guidelines for balancing BER performance and hardware efficiency in MLSE receiver DSP implementations for future high-speed wireline transceivers. © 2026 IEEE. 2026-05-25T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/60118 Title: A Spectral-Efficient Low-Power NRZ/PAM-4 Dual-Mode Wireline Transmitter for Multidrop Interfaces Author(s): Kim, Donggeon; Gharibdoust, Kiarash; Tajalli, Armin; Lee, Kyoungtae; Kim, Gain Abstract: This paper presents a reconfigurable and energy-efficient digital spectrum shaping signaling (DSSS) for multidrop interfaces, where the output spectrum of the transmitted data is shaped using the 2-times repetitive block transmission to avoid frequency notches in the multidrop channel, thereby achieving a data rate up to 4x the first channel notch frequency. In conventional wireline transceivers (TRX), compensating for frequency notches requires a large number of decision feedback equalizer (DFE) taps at the receiver, resulting in significant area and power overhead. In contrast, the proposed DSSS architecture supports spectrum-efficient reconfigurable dual-mode NRZ/PAM4, reducing required equalization efforts and improving energy efficiency. The proposed scheme and its transmitter (TX) were first validated through event-driven behavioral simulations using XMODEL and verified with equipment-based measurements. Post-layout simulation results in 28nm CMOS process demonstrated 4 Gb/s data rate communicating over a channel having its first > 30 dB notch at 1 GHz, with a 235mV vertical eye opening and a TX energy efficiency of 0.39 pJ/b at 0.8V supply. 2025-08-07T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/59886 Title: BIT ERROR CORRECTION APPARATUS FOR HIGH-SPEED WIRED INTERFACE Author(s): 최유진; 김가인 Abstract: A bit error correction apparatus for a high-speed wired interface, according to some embodiments, comprises: an FFE circuit that receives a digitized bit stream and generates an FFE output value; a decision circuit that generates a decision output value by performing a decision operation on the FFE output value; a reconfigured FFE circuit that generates a reconfigured FFE output value by performing FFE on the decision output value; a summer that calculates a difference value between the reconfigured FFE output value and the FFE output value; a comparator that determines whether or not an error has occurred in the bit stream, by comparing the difference value with a threshold value; and an error corrector that performs error correction on the bit stream, when it is determined that the error has occurred in the bit stream as a result of the determination performed by the comparator.