https://scholar.dgist.ac.kr/handle/20.500.11750/16129 2026-04-21T13:41:14Z https://scholar.dgist.ac.kr/handle/20.500.11750/60118 Title: A Spectral-Efficient Low-Power NRZ/PAM-4 Dual-Mode Wireline Transmitter for Multidrop Interfaces Author(s): Kim, Donggeon; Gharibdoust, Kiarash; Tajalli, Armin; Lee, Kyoungtae; Kim, Gain Abstract: This paper presents a reconfigurable and energy-efficient digital spectrum shaping signaling (DSSS) for multidrop interfaces, where the output spectrum of the transmitted data is shaped using the 2-times repetitive block transmission to avoid frequency notches in the multidrop channel, thereby achieving a data rate up to 4x the first channel notch frequency. In conventional wireline transceivers (TRX), compensating for frequency notches requires a large number of decision feedback equalizer (DFE) taps at the receiver, resulting in significant area and power overhead. In contrast, the proposed DSSS architecture supports spectrum-efficient reconfigurable dual-mode NRZ/PAM4, reducing required equalization efforts and improving energy efficiency. The proposed scheme and its transmitter (TX) were first validated through event-driven behavioral simulations using XMODEL and verified with equipment-based measurements. Post-layout simulation results in 28nm CMOS process demonstrated 4 Gb/s data rate communicating over a channel having its first > 30 dB notch at 1 GHz, with a 235mV vertical eye opening and a TX energy efficiency of 0.39 pJ/b at 0.8V supply. 2025-08-07T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/59886 Title: BIT ERROR CORRECTION APPARATUS FOR HIGH-SPEED WIRED INTERFACE Author(s): 최유진; 김가인 Abstract: A bit error correction apparatus for a high-speed wired interface, according to some embodiments, comprises: an FFE circuit that receives a digitized bit stream and generates an FFE output value; a decision circuit that generates a decision output value by performing a decision operation on the FFE output value; a reconfigured FFE circuit that generates a reconfigured FFE output value by performing FFE on the decision output value; a summer that calculates a difference value between the reconfigured FFE output value and the FFE output value; a comparator that determines whether or not an error has occurred in the bit stream, by comparing the difference value with a threshold value; and an error corrector that performs error correction on the bit stream, when it is determined that the error has occurred in the bit stream as a result of the determination performed by the comparator. https://scholar.dgist.ac.kr/handle/20.500.11750/59291 Title: A 144 mW 76 Gb/s DAC-Based Discrete Multitone Wireline Transmitter in 5nm FinFET Author(s): Jang, Seoyoung; Lee, Jaewon; Kossel, Marcel André; Brändli, Matthias; Morf, Thomas; Francese, Pier Andrea; Kim, Gain Abstract: This paper presents a 76 Gb/s digital-to-analog converter (DAC)-based discrete multitone (DMT) wireline transmitter (TX) fabricated in 5 nm FinFET. Bit and power loading with 32/64/128-QAM across 31 orthogonal subchannels is demon-strated over a channel with 9.7 dB insertion loss (IL), achieving a bit error rate (BER) of 2.1 E-4. The prototype consumes 144 mW from 0.675 V digital and 0.725 V analog supplies, resulting in an energy efficiency of 1.89 pJ/b. An on-chip DSP performs subchannel-wise bit/power allocation and spectral shaping using a 64-tap inverse fast Fourier transform (IFFT) and cyclic prefix (CP) insertion. Compared to conventional PAM-based TXs, the proposed architecture provides improved bandwidth efficiency and signal-to-noise ratio (SNR) through frequency-domain modulation and equalization. This work is the first demonstration of a DAC-based DMT TX at 76 Gb/s data rate fabricated in advanced CMOS technology. 2025-09-08T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/59290 Title: A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET Author(s): Lee, Jaewon; Francese, Pier-Andrea; Braendli, Matthias; Morf, Thomas; Kossel, Marcel; Jang, Seoyoung; Choi, Yujin; Kim, Donggeon; Jang, Taekwang; Kim, Gain Abstract: This article presents a 112-Gb/s discrete multitone (DMT) wireline receiver (RX) datapath with a 50-GS/s, 8-bit, 64-way ( 8x 8 ) time-interleaved time-based analog-to-digital converter (TI-TBADC) in a 5-nm FinFET. The TBADC converts the voltage input into a time-domain quantity using a ring oscillator (ROSC). Eight-slice TBADCs, driven from the same first-rank interleaver, share the identical injection-locked ROSC (IROSC) for voltage-to-time conversion (VTC). The DMT digital signal processor (DSP) achieves optimal bit and power loading with 63 orthogonal subchannels by employing a 64-way single-stage multi-path delay feedback (MDF) fast Fourier transform (FFT) core. An on-chip sign-sign least mean square (SS-LMS) engine adapts equalizer coefficients to combat channel fluctuation. The RX prototype demonstrates 4E-4 BER when communicating over the channel, exhibiting 18-dB insertion loss (IL) at Nyquist, while consuming 347-mW power and 0.242-mm(2) silicon area. 2025-12-31T15:00:00Z