https://scholar.dgist.ac.kr/handle/20.500.11750/16130 2026-04-04T15:59:28Z https://scholar.dgist.ac.kr/handle/20.500.11750/59290 Title: A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET Author(s): Lee, Jaewon; Francese, Pier-Andrea; Braendli, Matthias; Morf, Thomas; Kossel, Marcel; Jang, Seoyoung; Choi, Yujin; Kim, Donggeon; Jang, Taekwang; Kim, Gain Abstract: This article presents a 112-Gb/s discrete multitone (DMT) wireline receiver (RX) datapath with a 50-GS/s, 8-bit, 64-way ( 8x 8 ) time-interleaved time-based analog-to-digital converter (TI-TBADC) in a 5-nm FinFET. The TBADC converts the voltage input into a time-domain quantity using a ring oscillator (ROSC). Eight-slice TBADCs, driven from the same first-rank interleaver, share the identical injection-locked ROSC (IROSC) for voltage-to-time conversion (VTC). The DMT digital signal processor (DSP) achieves optimal bit and power loading with 63 orthogonal subchannels by employing a 64-way single-stage multi-path delay feedback (MDF) fast Fourier transform (FFT) core. An on-chip sign-sign least mean square (SS-LMS) engine adapts equalizer coefficients to combat channel fluctuation. The RX prototype demonstrates 4E-4 BER when communicating over the channel, exhibiting 18-dB insertion loss (IL) at Nyquist, while consuming 347-mW power and 0.242-mm(2) silicon area. 2025-12-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/58328 Title: A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform Author(s): Lee, Jaewon; Jang, Seoyoung; Choi, Yujin; Kim, Donggeon; Braendli, Matthias; Morf, Thomas; Kossel, Marcel; Francese, Pier-Andrea; Kim, Gain Abstract: This article presents a 2-lane 2 × 2 multiple-input, multiple-output (MIMO) 4-level pulse amplitude modulation (PAM-4) minimum mean-squared-error (MMSE)-decision-feedback equalizer (DFE) with far-end crosstalk (FEXT) cancellation for digital-to-analog converter (DAC)-/analog-to-digital converter (ADC)-based high-speed serial links. The receiver (RX) datapath is designed with a 15-tap MIMO feedforward equalizer (FFE) and a one-tap MIMO DFE with the least mean square (LMS), enabling adaptation to channel variation while maintaining the MMSE setting. The RX digital signal processor (DSP) place and route (PnR) in a 28-nm CMOS is estimated to consume 201 mW/lane at a 56-Gb/s/lane data rate while occupying a 0.5-mm2/lane silicon area. We further implement a real-time evaluation platform to verify the functionality of the MIMO PAM-4 MMSE-DFE with rapid bit-error-rate (BER) testing on RFSoC. The measurement result demonstrates that the MIMO MMSE-DFE significantly improves BER performance from 2.75e−3 to 1.31e−7 compared with equalization without FEXT cancellation when communicating over a channel exhibiting 12.4-dB insertion loss (IL) and 13.2-dB IL-to-crosstalk ratio (ICR) at Nyquist. © IEEE. 2025-05-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/58325 Title: An 86.71875-GHz RF Transceiver for 57.8125-Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28-nm CMOS Author(s): Choi, Hanho; Song, Ha-Il; Won, Hyosup; Yoo, Junyoung; Kwon, Woohyun; Jin, Huxian; Kwon, Konan; Lee, Cheongmin; Kim, Gain; Eu, Jake; Park, Sean; Bae, Hyeon-Min Abstract: This article presents an 86.71875-GHz RF transceiver IC featuring a fully integrated clock and data recovery (CDR)-assisted carrier synchronization loop (CSL) for waveguide links. The carrier frequency of 86.71875 GHz is chosen to be the third harmonic of the baseband null frequency of 28.90625 GHz, and the carrier synchronization is achieved using a baseband CDR instead of power-and area-intensive RF circuits. The IC, fabricated in 28-nm CMOS, demonstrates 57.8125-Gb/s pulse-amplitude modulation-4 (PAM-4) data transmission over a 1.5-m waveguide channel while improving the timing margin by 38% compared to conventional methods. The Tx and Rx ICs occupying an area of 1.98 × 0.95 mm2 consume 190.1 and 117 mW at 57.8125 Gb/s, respectively. The test chip achieves the figure of merit (FoM) of 3.5 pJ/b/m in terms of throughput–distance and energy efficiency. © IEEE. 2025-10-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/57467 Title: BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics Author(s): Lee, Jaehyun; Choi, Dong-Gu; Kim, Gain; Song, Minyoung; Yoon, Jong-Hyeok Abstract: Multi-agent (MA) simultaneous localization and mapping (SLAM) has been rigorously explored to enhance map accuracy in swarm robotics. Although centralized MA SLAM systems, which depend on a server for complex computations in map optimization, have been extensively studied, the circuit-domain approaches to decentralized MA SLAM systems are still limited due to challenges such as limited memory capacity and security vulnerabilities in wireless inter-agent data transmission. Thus, we propose a BEE-SLAM accelerator, a location-sharing MA neuromorphic SLAM accelerator inspired by bee communication for decentralized MA SLAM systems. The location-sharing-based MA error correction (MAEC) is employed to attain accurate map results without loop closure with a 94.81% reduced number of operations compared to the global map-based MA SLAM. In addition, a 7 × 7 pulsewidth modulation (PWM)-based hybrid mixed-signal/digital pose-cell (HY-PC) array with pseudo pose cells (PPCs) achieves 2.04 × energy efficiency compared to the oscillatory pose-cell array. The test chip fabricated in a 65-nm CMOS technology achieves a peak energy efficiency of 17.96 TOPS/W under 350 × 450 m outdoor exploration. © IEEE. 2025-02-28T15:00:00Z