https://scholar.dgist.ac.kr/handle/20.500.11750/46315 2026-10-22T09:59:38Z https://scholar.dgist.ac.kr/handle/20.500.11750/60976 Title: A Low-Jitter Double-Sampling PLL With Linearity Enhanced Inverter-Based gm Cell Author(s): Sim, Changmin; Kim, Seongcheol; Park, Seungwoo; So, Junseob; Shin, Hwaseok; Kim, Taehwan; Lee, Seon-Been; Song, Minyoung; Kim, Chulwoo Abstract: This article presents a double-sampling phase-locked loop (DSPLL) based on an inverter transconductance (g(m)) cell. A differential inverter-based g(m) cell with a constant-g(m) bias circuit is proposed to enhance linearity and suppress in-band phase noise (IBPN) without relying on a power-hungry charge pump or excessive reference buffer (RBUF) slew rate. In addition, compact duty-cycle corrector (DCC) and common-mode feedback (CMFB) circuits bias the g(m) cell's input and output to the inverter's trip point, ensuring the g(m) cell's dynamic range with an additional power overhead of only 39 & micro;W. Fabricated in a 28-nm CMOS process, the prototype DSPLL achieves 53.6-fs RMS jitter and a -54-dBc reference spur at a 16-GHz output while consuming 17.3 mW. Measurement results confirm the loop maintains stable linear dynamics under reference frequency up- and down-steps. 2026-09-30T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/60710 Title: 저전력 고선형 저잡음 증폭기 Author(s): 송민영; 박찬수 https://scholar.dgist.ac.kr/handle/20.500.11750/59196 Title: CONTINUOUS TIME DELTA SIGMA ANALOG-DIGITAL CONVERSION DEVICE CAPABLE OF SIMULTANEOUSLY MEASURING VOLTAGE AND CURRENT Author(s): 윤종혁; 송민영; 이정협; 설태령 Abstract: Disclosed is an analog-digital converter capable of simultaneously obtaining a voltage and a current. The disclosed analog-digital converter can simultaneously obtain a voltage and a current by using a hybrid integrator for simultaneously receiving and integrating the voltage and the current and a quantizer for generating a differential mode output and a common mode output through comparison with a reference voltage. By using the analog-digital converter according to an exemplary embodiment, the size of a system can be maintained small while consuming less power, and thus a biometric response can be easily identified and analyzed. https://scholar.dgist.ac.kr/handle/20.500.11750/58567 Title: Design and Analysis of ΔΣ Modulator Analogous Bang-Bang Digital PLL Author(s): Park, Minsu; Yoon, Jong-Hyeok; Song, Minyoung Abstract: This paper presents the analysis and design methodology of a second-order ΔΣ modulator analogous bang-bang digital phase-locked loop (DSBPLL). When the bang-bang-based digital PLL (BB-DPLL) cannot fully track the DCO jitter, the jitter slewing effect exacerbates the in-band noise. The proposed DSBPLL can increase the PLL filter order without using a high-order loop filter, thereby mitigating the in-band noise caused by input tracking jitter. Theoretical noise analysis confirmed that the proposed DSBPLL can reduce 54.3% of the integrated jitter from 100 kHz to 100 MHz, consistent with the measurement results. 2025-12-31T15:00:00Z