https://scholar.dgist.ac.kr/handle/20.500.11750/56975 2026-11-11T11:05:21Z https://scholar.dgist.ac.kr/handle/20.500.11750/61150 Title: Systematic optimization of low-temperature ALD ZnO thin-film transistors with epoxy interlayer toward monolithic 3D integration Author(s): Park, Heechang; Lee, Jeonghun; Jang, Jeonggyun; Pyo, Goeun; Kwon, Hyuk-Jun; Lee, Byeongmoon; Shin, Jeong Hee; Jang, Jae Eun Abstract: Monolithic three-dimensional (3D) integration of thin-film transistors (TFTs) above silicon platforms is uniquely enabled when every back-end-of-line step can be confined below 200 degrees C, a thermal budget that opens the door to polymer interlayers as stacking spacers, an option foreclosed to higher-temperature oxide-TFT systems. ZnO grown by atomic layer deposition (ALD) is one of the few channel materials compatible with this constraint, yet operating at the sub-200 degrees C limit narrows the process window for each step (channel growth, post-deposition treatment, dielectric-channel interface, and structural interlayer) and how these steps jointly determine stackrelevant device behavior has not been fully resolved. We present a unified optimization study that holds the entire process flow within this sub-200 degrees C envelope while addressing all four steps in a single platform. On the mechanistic side, co-sweeping film thickness (15-55 nm) and air-anneal duration (0-180 min) identified a 30-nm channel annealed for 60 min as the operating point delivering the lowest subthreshold slope (97.8 mV dec(-1)) and the smallest combined bias-stress drift (| Delta V-th| = 1.10 V); O 1 s X-ray photoelectron spectra revealed that the V-O-related oxygen-deficient signal continues to shrink past 60 min while electrical metrics worsen, suggesting that defect balance, rather than defect minimization, better captures the conditions for optimal performance. On the application side, ozone post-treatment of HfO2 suppresses interface frequency dispersion to 2.28 % (vs. 140 % untreated), and an epoxy resin-based polymer interlayer enables top-stack ZnO TFTs that match identically processed reference devices on a Si substrate within Delta V-th approximate to +12 mV. This polymer-based stacking route contrasts with the inorganic interlayers (SiO2, HfO2, Al2O3) more commonly used in prior oxide-TFT stacking studies. These findings collectively outline a coherent, fully sub-200 degrees C pathway toward a polymer-ready monolithic ZnO TFT stack. 2026-12-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/61071 Title: Simultaneous Enhancement of Performance and Stability in Dual-Gate a-IGZO Thin-Film Transistors via Single-Step Laser Annealing for Capacitor-Less DRAM Author(s): 권시현; Kim, Junil; Park, Geuntae; Kim, Minseok; Hwang, Woohyun; Kim, Wanki; Ha, Daewon; Lee, Byeongmoon; Jang, Jae Eun; Kwon, Hyuk-Jun Abstract: Wide-bandgap amorphous oxide semiconductors (AOSs), particularly indium-gallium-zinc-oxide (IGZO), offer ultralow off-current and back-end-of-line compatibility, making them attractive for advanced dynamic random access memory (DRAM). In capacitor-less two-transistor (2T0C) DRAM, dual-gate (DG) a-IGZO TFTs are promising read transistors, but achieving a stable positive threshold voltage (V-th) typically reduces field-effect mobility (& micro;(FE)) and increases contact resistance (R-C), limiting fast operation. This study introduces a spatially selective laser annealing strategy that overcomes this limitation in a single step. The steep thermal gradient promotes oxygen incorporation at the top-gate dielectric/channel interface, passivating defects without severely depleting carrier density. Simultaneously, WOx interlayer removal combined with oxygen redistribution forms conductive n(+) regions at source/drain contacts. This dual modification stabilizes the channel and reduces R-C, enabling both high & micro;(FE) (37.9 cm(2) V-1 s(-1)) and a stable positive V-th (0.27 V). The optimized devices exhibit small Delta V-th under bias stress and reliable operation, demonstrating the read function of 2T0C DRAM, maintaining stable "0/1" state discrimination and wide memory windows (>10(5)) for over 10 000 s. This single-step process provides a practical route to overcome the performance-stability trade-off in AOS TFTs, highlighting strong potential for emerging memory applications. 2026-09-30T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/60480 Title: Laser-Induced Oxygen Engineering for Localized Homojunction Formation in SnS2 Photodetectors Author(s): Lee, Jieun; Kim, Junil; Sim, Young-Jun; Lee, Byeongmoon; Jang, Jae Eun; Kwon, Hyuk-Jun Abstract: The development of high-performance optoelectronic devices based on 2D materials has attracted significant attention. However, conventional vertical stacking methods are limited by complex processes and interfacial defects. To overcome these challenges, we propose a simple and efficient one-step process to form an in-plane homojunction within a single n-type tin disulfide (SnS2) flake via direct laser irradiation. The core process, oxidative thinning, utilizes a focused 532 nm laser to locally convert a portion of SnS2 into tin oxide (SnOx). Consequently, an energy barrier arising from a work-function difference of approximately 0.7 eV is formed at the interface, promoting the separation of photogenerated electron-hole pairs. The fabricated photodetector demonstrates a fast response time (tau r/tau f = 474/299 ms), an improvement of several tens of times compared with the pristine SnS2 device. Furthermore, it exhibits a high responsivity (R) of 703 mA W-1, an external quantum efficiency (EQE) of 170%, and a remarkable specific detectivity (D*) of 2.35 x 1014 Jones, along with excellent operational stability. This laser-induced local conversion technique presented can provide a powerful and practical platform for developing next-generation flexible and wearable optoelectronic devices. 2026-04-30T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/59972 Title: Hole Current Enhancement Using W1-x Cr x Se2 Alloy Interface for p-Type WSe2 FETs Author(s): Sim, Young-Jun; Kim, Junil; Lee, Jieun; Lee, Byeongmoon; Jang, Jae Eun; Kwon, Hyuk-Jun Abstract: Two-dimensional (2D) transition-metal dichalcogenides (TMDs) have emerged as promising candidates for next-generation semiconductor devices. Among TMDs, tungsten diselenide (WSe2) is regarded as an ideal material for p-type field-effect transistors (FETs). However, the realization of high-performance p-type devices remains limited due to undesired ambipolar behavior and high contact resistance. These challenges originate from Fermi level pinning (FLP) caused during conventional deposition processes. Although van der Waals (vdW) contacts have been introduced to overcome FLP, their implementation faces difficulties due to contamination-induced degradation and limitations in CMOS process compatibility. In this study, we demonstrate a scalable approach for p-type contact via the W1-xCrxSe2 alloy interface. It has been reported that Cr incorporation reduces the bandgap of WSe2, while CrxSey exhibits p-type semimetal properties. Leveraging these properties, thermal annealing of Cr contacts enables the formation of WSe2/W1-xCrxSe2/Cr layers at the contact region. This interfacial alloy effectively suppresses FLP, eliminates undesirable ambipolar behavior, and enhances hole injection. The resulting devices achieve a Schottky barrier height as low as 61.1 meV and reduce contact resistance by approximately 3 orders of magnitude. Consequently, W1-xCrxSe2 alloy interface contact WSe2 FETs exhibit robust p-type performance with an average on/off current ratio of 2.19 x 10(8) across 20 devices. These findings present a practical and scalable strategy for engineering low-resistance p-type contacts in WSe2, providing an important step toward the integration of TMD-based complementary logic in future scaled CMOS technologies. 2025-11-30T15:00:00Z