https://scholar.dgist.ac.kr/handle/20.500.11750/861 2026-04-04T14:59:02Z https://scholar.dgist.ac.kr/handle/20.500.11750/58978 Title: An Energy-Efficient Supply- and Temperature-Independent ΔΣ Capacitance-to-Digital Converter Author(s): Lee, Junghyup Abstract: Capacitance-to-digital converters (CDCs) are widely used for measuring pressure, humidity and acceleration [1–3] in a myriad of biomedical and IoT applications, where energy-efficiency and robustness against supply and temperature variations are of paramount importance. For instance, a wirelessly powered device will need to maintain its sensing accuracy in the presence of a varying supply voltage festered with digital switching noise. On the other hand, stand-alone IoT devices may need to sense variables accurately in varying ambient temperatures and battery supply voltage levels. In both cases, energy efficiency is a key requirement to sustain long-term device operation from a battery. Given the stringent limitations on the form-factor, such systems often need to employ small-sized, low-sensitivity sensors, necessitating the CDC to have a high sensing resolution. Among the previously proposed CDCs, the SAR-CDC [1] achieves high-energy efficiency. However, its input bridge is directly dependent and hence sensitive to supply voltage variations and supply-noise. Secondly, the resolution is only ∼6fF, despite the high energy efficiency. Several recent works have adopted time-domain CDCs employing a VCO quantizer to achieve high-resolution at low power. A SAR-VCOΔΣ CDC [2] reported high energy efficiency along with ∼1fF resolution that needed calibration to maintain accuracy followed by a closed-loop two-step SAR-TDΔΣ CDC [3] avoided the need for calibration. Still, these architectures are susceptible to supply and temperature effects, especially when they vary over a wide range. To solve these issues, we propose a time-locked ΔΣ CDC (TLΔΣ CDC) w hose output is derived from a VCO w hose period is locked to a precise external clock TREF. Furthermore, the VCO is time-locked by regulating its local supply and ground, making it insensitive against any variations in the chip-level supply. Multi-bit counters are used for the generation of the output, with the aim to reduce the time-quantization error and reduce the overall power by lowering the sampling frequency. As a result, the proposed TLΔΣ CDC can achieve the state-of-the-art FOMS=2.54μJ∙ppm2, supply sensitivity of ±0.55%/V over 1.2-2.2V and temperature sensitivity of 49.1ppm/°C over -20°C and 125°C. The sensing resolution is 70.5aF. Implemented in a 0.18μm standard CMOS process, the TLΔΣ CDC consumes 42.76μW from a 1.2V supply and 0.2mm2 active area. 2022-08-29T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/57946 Title: A 65nm 687.5-TOPS/W Drive Strength-based SRAM Compute-In-Memory Macro with Adaptive Dynamic Range for Edge AI applications Author(s): Choi, Dong-Gu; Lee, Jaehyun; Koo, Jahyun; Han, Woo Kyoung; Park, Dahoon; Kung, Jaeha; Lee, Junghyup; Yoon, Jong-Hyeok Abstract: Analog compute-in-memory (ACIM) has been intensively investigated, pursuing better energy efficiency, network accuracy, and compatibility with various AI models [1-5]. In particular, SRAM-based ACIM macros achieve the flexibility of input/weight (IN/W) allocation incorporating bit-serial inputs, bitwise weight loading across multiple bitlines (BL), and digital shift-and-add multiplication of partial sum (PSUM) in the output line (OL). However, shift-and-add multiplication inevitably exacerbates the PSUM errors arising from the computing/readout process under device mismatches and a limited sensing margin (SM) in ACIM (Fig. 1). This leads to severely erroneous MAC outputs and substantial accuracy loss, impeding the practical utilization of ACIM. To mitigate the Psum errors, the ACIM macro with high-precision IN/W and truncation at the MAC output was proposed [4]. The truncation filters out the quantization noise to an extent, thereby attaining the mitigated accuracy loss. Nevertheless, prior work still suffers from PSUM errors due to limited VLSB of high-resolution ADCs. Furthermore, the truncated MAC outputs undermine the advantages of high-precision IN/W undergoing frequent weight updates in ACIM macros. An alternative approach is using a low-resolution ADC with quantization for PSUM to secure higher VLSB and suppress the resultant PSUM error [5]. However, under high macro utilization, it eventually suffers from accuracy loss due to quantization error, which is amplified by the shift and adder. To address the challenges, the drive strength-based SRAM compute-in-memory (DS-CIM) macro is proposed featuring: 1) 6b drive strength-mode sensing with adaptive dynamic range that secures up to 39.2x-boosted sensing margin and 97% of error-free Psum readout on 2's-complement 4b-IN/W ResNet-20 benchmarks, 2) row-wise adaptive dynamic range SAR (ADR-SAR) logic enabling concurrent ADC readout at every OL with the area efficiency of 15.83 TOPS/mm2, 3) input-aware binary search (IABS) reducing average ADC conversion cycles by 64% on the ResNet-20 benchmark, and 4) a heterogeneous logic unit (HLU) for column-wise logic reconfigurability. © 2024 IEEE. 2024-11-18T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/57859 Title: A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO−ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition Author(s): Lee, Sehwan; Seol, Taeryoung; Kim, Geunha; Song, Minyoung; Kim, Gain; Yoon, Jong-Hyeok; George, Arup K.; Lee, Junghyup Abstract: This paper proposes a 97dB-PSRR, 178.4dB-FOMDR calibration-free 16-channel VCO-ΔΣ ADC system using a PVT-insensitive frequency-locked differential regulation (FLDR) scheme suitable for wireless ExG Acquisition. Thanks to the FLDR, the SNDR degradation in all 16 channels is less than 1dB over 1.4-2V supply and 20-60°C temperature ranges. Implemented in a 0.18μm standard CMOS process, the proposed system consumes 172μW from a 1.4V supply and occupies 2.7mm2 active area, while a single channel consumes 4.2μW and 0.12mm2, respectively. © 2024 IEEE. 2024-06-17T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/57832 Title: 3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C from -20°C to 125°C Author(s): Park, Pangi; Lee, Junghyup; Cho, Seonghwan Abstract: Improving the temperature stability of the reference current (IREF) is essential for the reliable operation of precision electronics for various applications, including automotive and industrial sensors. There are several approaches to generate a temperature-stable IREF, which include a weighted sum of PTAT and CTAT currents, dividing a reference voltage by a resistor with a similar temperature coefficient (TC) [1-3], and biasing a MOSFET at its zero-temperature-coefficient bias point [4]. While these techniques can remove the first-order TC, the remaining curvature due to the second-order TC limits the achievable temperature stability. In [5], the curvature in a reference current is corrected by using a curvature-corrected bandgap reference voltage and a switched capacitor resistor. However, it requires a stable and bulky reference oscillator (e.g., crystal). © 2024 IEEE. 2024-02-18T15:00:00Z