https://scholar.dgist.ac.kr/handle/20.500.11750/91 2026-11-11T10:50:38Z https://scholar.dgist.ac.kr/handle/20.500.11750/61156 Title: Biomimetic artificial olfactory systems based on metal-organic frameworks: from material design to intelligent pattern recognition Author(s): Lim, Hyeongtae; Kwon, Hyuk-Jun Abstract: Artificial olfactory systems (AOS) capable of mimicking biological olfaction are emerging as powerful tools for complex gas analysis. However, conventional sensing materials often face limitations regarding selectivity, response speed, and high operating temperatures. Metal-organic frameworks (MOFs) offer an ideal solution to these challenges due to their ultra-high porosity and tunable chemical functionality. This review presents a comprehensive overview of strategies to implement high-performance MOF-based AOS. First, we systematically examine three material categories—pristine MOFs, MOF-based composites, and MOF-derivatives—highlighting how their structural design enhances sensitivity and response diversity. Beyond hardware, this review bridges the gap between material synthesis and intelligent pattern recognition. We discuss the integration of machine learning algorithms, ranging from unsupervised clustering to advanced deep learning techniques, which are essential for decoding high-dimensional odor data. Finally, critical challenges for real-world deployment, including humidity stability, large-area fabrication, and sensor drift, are addressed, along with potential solutions. By converging innovative MOF design with advanced pattern recognition, this review provides a roadmap for developing next-generation intelligent machine olfaction for applications in healthcare, environmental monitoring, and smart industries. 2026-12-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/61150 Title: Systematic optimization of low-temperature ALD ZnO thin-film transistors with epoxy interlayer toward monolithic 3D integration Author(s): Park, Heechang; Lee, Jeonghun; Jang, Jeonggyun; Pyo, Goeun; Kwon, Hyuk-Jun; Lee, Byeongmoon; Shin, Jeong Hee; Jang, Jae Eun Abstract: Monolithic three-dimensional (3D) integration of thin-film transistors (TFTs) above silicon platforms is uniquely enabled when every back-end-of-line step can be confined below 200 degrees C, a thermal budget that opens the door to polymer interlayers as stacking spacers, an option foreclosed to higher-temperature oxide-TFT systems. ZnO grown by atomic layer deposition (ALD) is one of the few channel materials compatible with this constraint, yet operating at the sub-200 degrees C limit narrows the process window for each step (channel growth, post-deposition treatment, dielectric-channel interface, and structural interlayer) and how these steps jointly determine stackrelevant device behavior has not been fully resolved. We present a unified optimization study that holds the entire process flow within this sub-200 degrees C envelope while addressing all four steps in a single platform. On the mechanistic side, co-sweeping film thickness (15-55 nm) and air-anneal duration (0-180 min) identified a 30-nm channel annealed for 60 min as the operating point delivering the lowest subthreshold slope (97.8 mV dec(-1)) and the smallest combined bias-stress drift (| Delta V-th| = 1.10 V); O 1 s X-ray photoelectron spectra revealed that the V-O-related oxygen-deficient signal continues to shrink past 60 min while electrical metrics worsen, suggesting that defect balance, rather than defect minimization, better captures the conditions for optimal performance. On the application side, ozone post-treatment of HfO2 suppresses interface frequency dispersion to 2.28 % (vs. 140 % untreated), and an epoxy resin-based polymer interlayer enables top-stack ZnO TFTs that match identically processed reference devices on a Si substrate within Delta V-th approximate to +12 mV. This polymer-based stacking route contrasts with the inorganic interlayers (SiO2, HfO2, Al2O3) more commonly used in prior oxide-TFT stacking studies. These findings collectively outline a coherent, fully sub-200 degrees C pathway toward a polymer-ready monolithic ZnO TFT stack. 2026-12-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/61137 Title: Multifunctional tactile sensor system for tactile recorder Author(s): 장정균; 김동수; Sim, Min Kyung; Kang, Min Soo; Shin, Kwonsik; Lee, Junghyup; Kang, Hongki; Kwon, Hyuk-Jun; Jang, Jae Eun Abstract: Recent advances in robotic systems have enabled ultrafine control and precision comparable to that of human hands. However, structural constraints of robotic hands require tactile sensors with high functional complexity and precision while maintaining a simple design. Analogous to vision sensors, tactile sensors would benefit from the ability to record key tactile parameters, including pressure, temperature, and surface texture. This study presents a multifunctional tactile sensor integrating a piezoelectric pressure sensor and a resistive temperature sensor within a single body, along with a tactile recorder system for real-time data acquisition and analysis. The temperature sensor's electrodes also serve as those of the pressure sensor, achieving structural integration but functional separation. The sensor exhibits a response time of less than 10 ms and sensitivities of 0.69 mV/kPa and 2.7 Omega/degrees C for pressure and temperature, respectively. A deviation of 4.68 mV across 25 sensing cells demonstrates excellent uniformity, enabling high-resolution surface mapping and 3D topography rendering. An experimentally derived compensation formula minimizes pyroelectric-induced errors, ensuring accurate pressure readout under varying temperatures. The tactile recorder visualizes and stores signals for subsequent analysis of surface texture and temperature-dependent tactile responses. This work demonstrates a structurally simple yet functionally rich platform for tactile sensing and recording in artificial tactile interfaces. 2026-10-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/61128 Title: A Low-Latency Reconstruction-Based Symbol Error Correction for PAM-4 DSP-Based Wireline Receivers Author(s): 최유진; Kim, Donggeon; 장서영; 김성진; 권도현; Braendli, Matthias; Lee, Jaewon; Morf, Thomas; Kossel, Marcel; Tokgoz, Korkut Kaan; Francese, Pier-Andrea; Kim, Gain Abstract: This paper proposes a decision-error correction scheme that improves the pre-forward error correction (pre-FEC) bit-error rate (BER) by identifying and correcting symbol errors after the decision feedback equalizer (DFE) without introducing any coding overhead. The proposed method reconstructs the received waveform to localize error-prone symbols without requiring additional redundancy and performs symbol-level correction by exploiting intrinsic properties of pulse-amplitude modulation (PAM) signaling. The error detection and correction scheme is implemented using simple digital arithmetic and logic and completes the correction process within three digital signal processor (DSP) clock cycles, thereby avoiding excessive latency. A 4-level pulse-amplitude modulation (PAM-4) DSP employing a 64-way parallel datapath was implemented in a 14-nm FinFET process, occupying 0.269 mm(2) and targeting an 875 MHz clock frequency. The design was validated on a Xilinx ZCU111 RFSoC platform, demonstrating a BER improvement of more than five orders of magnitude at 4.8 Gb/s over a channel with 22.9 dB insertion loss (IL) at Nyquist. 2026-10-31T15:00:00Z