https://scholar.dgist.ac.kr/handle/20.500.11750/10177 Sat, 04 Apr 2026 17:30:02 GMT 2026-04-04T17:30:02Z https://scholar.dgist.ac.kr/handle/20.500.11750/56400 Title: CPWG-fed reconfigurable beam steering antenna using dipole and loop combined structure Author(s): Ha, S. -J.; Kim, J. -Y.; Kim, Y. -J.; Park, Tae Joon; Lee, B. -J.; Jung, C. W. Abstract: This paper proposes a coplanar waveguide with lower ground (CPWG)-fed reconfigurable beam steering antenna using a bended dipole and circular loop combined structure. The radiation patterns of the antenna head towards specific directions when the dipole and loop antenna are combined at a reasonable ratio. The proposed antenna can steer the beam directions by controlling two RF switches (PIN diode). The maximum beam directions are +30°, 0°, and -30° in the azimuth plane, and the overall gains are 4.0-5.4 dBi in the operation bandwidth of 2.39-2.59 GHz. © 2012 Taylor & Francis. Sat, 31 Dec 2011 15:00:00 GMT https://scholar.dgist.ac.kr/handle/20.500.11750/56400 2011-12-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/13380 Title: 사이버물리시스템의 현재와 미래: 응용 어플리케이션 관점에서의 접근 Author(s): 원명규; 박태준; 손상혁 Abstract: 사이버물리시스템 (Cyber Physical Systems, CPS)은 우리가 살아가는 물리 세계와 센서, 엑츄에이터, 임베디드 컴퓨팅 시스템 등으로 구성된 사이버 세계와의 융합을 추구하는 새로운 패러다임이다. 본고에서는 CPS가 무엇인지, 왜 중요한지, 그리고 풀어야 할 숙제는 무엇인지에 대한 논의를 CPS 응용 어플리케이션의 관점에서 접근해본다. 특히 CPS 핵심 응용 분야 중 교통, 의료, 전력시스템과 관련하여 현재 대구경북과학기술원의 CPS글로벌센터에서 수행 되고 있는 연구와 그러한 연구의 기여도에 초점을 맞추어 논의를 진행한다. 즉 본고에서는 지능형 교통 시스템, 스마트 홈, 스마트 그리드 및 미래의 헬스케어 시스템에 관한 연구 소개를 통하여 CPS에 대한 실질적인 이해를 돕고 앞으로 CPS 연구와 관련하여 나아가야 할 방향에 대하여 논의한다. Sat, 31 Aug 2013 15:00:00 GMT https://scholar.dgist.ac.kr/handle/20.500.11750/13380 2013-08-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/13356 Title: High Bandwidth Efficiency and Low Power Consumption Walsh Code Implementation Methods for Body Channel Communication Author(s): Ho, Chee Keong; Cheong, Jia Hao; Lee, Junghyup; Kulkarni, Vishal; Li, Peng; Liu, Xin; Je, Min Kyu Abstract: With the growing number of wearable devices and applications, there is an increasing need for a flexible body channel communication (BCC) system that supports both scalable data rate and low power operation. In this paper, a highly flexible frequency-selective digital transmission (FSDT) transmitter that supports both data scalability and low power operation with the aid of two novel implementation methods is presented. In an FSDT system, data rate is limited by the number of Walsh spreading codes available for use in the optimal body channel band of 40-80 MHz. The first method overcomes this limitation by applying multi-level baseband coding scheme to a carrierless FSDT system to enhance the bandwidth efficiency and to support a data rate of 60 Mb/s within a 40-MHz bandwidth. The proposed multi-level coded FSDT system achieves six times higher data rate as compared to other BCC systems. The second novel implementation method lies in the use of harmonic frequencies of a Walsh encoded FSDT system that allows the BCC system to operate in the optimal channel bandwidth between 40-80 MHz with half the clock frequency. Halving the clock frequency results in a power consumption reduction of 32%. The transmitter was fabricated in a 65-nm CMOS process. It occupies a core area of 0.24×, 0.3 mm2. When operating under a 60-Mb/s data-rate mode, the transmitter consumes 1.85 mW and it consumes only 1.26 mW when operating under a 5-Mb/s data-rate mode. © 2014 IEEE. Sun, 31 Aug 2014 15:00:00 GMT https://scholar.dgist.ac.kr/handle/20.500.11750/13356 2014-08-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/13355 Title: A Reference-Less Injection-Locked Clock-Recovery Scheme for Multilevel-Signaling-Based Wideband BCC Receivers Author(s): Kulkarni, Vishal V.; Lee, Junghyup; Zhou, Jun; Ho, Chee Keong; Cheong, Jia Hao; Toh, Wei-Da; Li, Peng; Liu, Xin; Je, Min Kyu Abstract: Body channel communication (BCC) integrated circuits for emerging wireless body area network multimedia applications call for the need of high-speed inter-device data communication at ultra-low-power consumption and smaller device footprint. In this paper, a novel low-power injection-locking-based clock-recovery circuit (CRC) is proposed for BCC transceivers that employ multilevel direct digital signaling for high data rates. The CRC utilizes transition detection for generating pulses from transmitted digital data and injects them directly into the VCO to recover the clock. The pulse-based direct injection-locking architecture achieves instantaneous clock recovery from random multilevel data with a sensitivity of up to-43 dBm, and eliminates the need for a reference crystal used in conventional phase-locked-loop-based CRC circuits. Measured results verify that the proposed CRC achieves clock recovery for two-and three-level signals for data rates up to 160 Mb/s. Implemented in 65-nm CMOS technology, the CRC consumes 0.84 mW with a footprint of 0.122. © 2014 IEEE. Sun, 31 Aug 2014 15:00:00 GMT https://scholar.dgist.ac.kr/handle/20.500.11750/13355 2014-08-31T15:00:00Z