https://scholar.dgist.ac.kr/handle/20.500.11750/121 Mon, 03 Aug 2026 09:33:57 GMT 2026-08-03T09:33:57Z https://scholar.dgist.ac.kr/handle/20.500.11750/60546 Title: Inkjet-Printed BaTiO3 Nanoparticle-Embedded Capacitor Array for Physical Unclonable Function Author(s): Hong, Woongki; Bissannagari, Murali; Cho, Youngjae; Jang, Jae Eun; Kwon, Hyuk-Jun; Kang, Hongki Abstract: Nanoparticle (NP)-based physical unclonable functions (PUFs) have attracted attention as a digital fingerprint technology that alternates with microfabrication-based PUFs by utilizing natural randomness at the nanoscale. Mostly NP-based optical PUFs have been proposed due to the absence of nanomaterial fabrication method compatible with microelectronics, but the need for a bulky optical readout system makes it difficult to utilize them in microelectronics. In this work, we developed the NP-based capacitor PUF (CAP-PUF) technology that can be read electrically and integrated into microelectronics while utilizing the benefit of the natural physical randomness of NPs. We incorporated a high-k BaTiO3 NP inkjet printing micropatterning process for the fabrication of the NP-embedded CAP-PUF array. The inkjet-printing parameters have been optimized to maximize the natural randomness of the BaTiO3 NP micropatterns by increasing the intrinsic stochasticity, especially the fluid dynamics that occurring during the multilayer printing. The BaTiO3 NP-embedded CAP-PUF array shows high security performance, showing the inter-hamming distance of 0.52, uniformity of 0.44, entropy of 0.989, and intra-hamming distance up to 0.064. High-k NP inkjet-printing-based CAP-PUFs can provide highly unique digital fingerprints based on the intrinsic randomness in nanoscale for microelectronics. Sun, 31 May 2026 15:00:00 GMT https://scholar.dgist.ac.kr/handle/20.500.11750/60546 2026-05-31T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/60480 Title: Laser-Induced Oxygen Engineering for Localized Homojunction Formation in SnS2 Photodetectors Author(s): Lee, Jieun; Kim, Junil; Sim, Young-Jun; Lee, Byeongmoon; Jang, Jae Eun; Kwon, Hyuk-Jun Abstract: The development of high-performance optoelectronic devices based on 2D materials has attracted significant attention. However, conventional vertical stacking methods are limited by complex processes and interfacial defects. To overcome these challenges, we propose a simple and efficient one-step process to form an in-plane homojunction within a single n-type tin disulfide (SnS2) flake via direct laser irradiation. The core process, oxidative thinning, utilizes a focused 532 nm laser to locally convert a portion of SnS2 into tin oxide (SnOx). Consequently, an energy barrier arising from a work-function difference of approximately 0.7 eV is formed at the interface, promoting the separation of photogenerated electron-hole pairs. The fabricated photodetector demonstrates a fast response time (tau r/tau f = 474/299 ms), an improvement of several tens of times compared with the pristine SnS2 device. Furthermore, it exhibits a high responsivity (R) of 703 mA W-1, an external quantum efficiency (EQE) of 170%, and a remarkable specific detectivity (D*) of 2.35 x 1014 Jones, along with excellent operational stability. This laser-induced local conversion technique presented can provide a powerful and practical platform for developing next-generation flexible and wearable optoelectronic devices. Thu, 30 Apr 2026 15:00:00 GMT https://scholar.dgist.ac.kr/handle/20.500.11750/60480 2026-04-30T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/59972 Title: Hole Current Enhancement Using W1-x Cr x Se2 Alloy Interface for p-Type WSe2 FETs Author(s): Sim, Young-Jun; Kim, Junil; Lee, Jieun; Lee, Byeongmoon; Jang, Jae Eun; Kwon, Hyuk-Jun Abstract: Two-dimensional (2D) transition-metal dichalcogenides (TMDs) have emerged as promising candidates for next-generation semiconductor devices. Among TMDs, tungsten diselenide (WSe2) is regarded as an ideal material for p-type field-effect transistors (FETs). However, the realization of high-performance p-type devices remains limited due to undesired ambipolar behavior and high contact resistance. These challenges originate from Fermi level pinning (FLP) caused during conventional deposition processes. Although van der Waals (vdW) contacts have been introduced to overcome FLP, their implementation faces difficulties due to contamination-induced degradation and limitations in CMOS process compatibility. In this study, we demonstrate a scalable approach for p-type contact via the W1-xCrxSe2 alloy interface. It has been reported that Cr incorporation reduces the bandgap of WSe2, while CrxSey exhibits p-type semimetal properties. Leveraging these properties, thermal annealing of Cr contacts enables the formation of WSe2/W1-xCrxSe2/Cr layers at the contact region. This interfacial alloy effectively suppresses FLP, eliminates undesirable ambipolar behavior, and enhances hole injection. The resulting devices achieve a Schottky barrier height as low as 61.1 meV and reduce contact resistance by approximately 3 orders of magnitude. Consequently, W1-xCrxSe2 alloy interface contact WSe2 FETs exhibit robust p-type performance with an average on/off current ratio of 2.19 x 10(8) across 20 devices. These findings present a practical and scalable strategy for engineering low-resistance p-type contacts in WSe2, providing an important step toward the integration of TMD-based complementary logic in future scaled CMOS technologies. Sun, 30 Nov 2025 15:00:00 GMT https://scholar.dgist.ac.kr/handle/20.500.11750/59972 2025-11-30T15:00:00Z https://scholar.dgist.ac.kr/handle/20.500.11750/59971 Title: Heterojunction Wide-Bandgap Amorphous Metal Oxide High-Voltage Thin-Film Transistors with High Driving Current and Low Process Temperature Author(s): Lee, Jungha; Lee, Junhee; Kim, Duhee; Kwon, Hyuk-Jun; Jang, Jae Eun; Kang, Hongki Abstract: The implementation of high-voltage (HV) applications in monolithic integration has led to increased demand for wide-bandgap high-voltage thin-film transistors (HVTFTs) to solve voltage mismatch problems between HV devices and complementary metal oxide semiconductor (CMOS) integrated circuits. However, typical HVTFTs possess several limitations, including low driving current due to the drain offset structure and high process temperature (>300 degrees C), limiting high-frequency switching operation and flexible substrate compatibility, thus impeding their application in flexible and wearable HV electronics. This study presents heterojunction wide-bandgap channel-based HVTFTs fabricated using amorphous indium tin zinc oxide (a-ITZO) and indium gallium zinc oxide (a-IGZO) to overcome the limitations of the current HVTFTs. Owing to the heterojunction channel layer, we achieved a much higher driving current of >0.37 mA/mm (I-D/W) at V-GS = 210 V and V-DS = 5 V with a flexible-electronics-compatible channel layer annealing temperature (150 degrees C), indicating that the TFTs can be even applied in HV flexible/wearable electronics. Therefore, ITZO/IGZO TFTs can withstand considerably higher power than single-layer IGZO HVTFTs, while exhibiting similar HV breakdown characteristics. Additionally, the ITZO/IGZO HVTFTs demonstrate superior electrical stability under high-voltage-bias conditions compared to conventional IGZO HVTFTs. Thus, heterojunction amorphous metal oxide TFTs are suitable for fast switching flexible HV electronic systems while gate-controlled by CMOS technologies. Sun, 30 Nov 2025 15:00:00 GMT https://scholar.dgist.ac.kr/handle/20.500.11750/59971 2025-11-30T15:00:00Z