https://scholar.dgist.ac.kr/handle/20.500.11750/16132 Tue, 21 Apr 2026 15:10:20 GMT 2026-04-21T15:10:20Z https://scholar.dgist.ac.kr/handle/20.500.11750/59886 Title: BIT ERROR CORRECTION APPARATUS FOR HIGH-SPEED WIRED INTERFACE Author(s): 최유진; 김가인 Abstract: A bit error correction apparatus for a high-speed wired interface, according to some embodiments, comprises: an FFE circuit that receives a digitized bit stream and generates an FFE output value; a decision circuit that generates a decision output value by performing a decision operation on the FFE output value; a reconfigured FFE circuit that generates a reconfigured FFE output value by performing FFE on the decision output value; a summer that calculates a difference value between the reconfigured FFE output value and the FFE output value; a comparator that determines whether or not an error has occurred in the bit stream, by comparing the difference value with a threshold value; and an error corrector that performs error correction on the bit stream, when it is determined that the error has occurred in the bit stream as a result of the determination performed by the comparator. https://scholar.dgist.ac.kr/handle/20.500.11750/59886 https://scholar.dgist.ac.kr/handle/20.500.11750/59182 Title: LOOP-BREAK DECISION FEEDBACK EQUALIZER Author(s): 김동건; 김가인 Abstract: The present invention relates to a loop-break decision feedback equalizer and, more specifically, to a technology designed to split each parallel way of an analog-to-digital converter (ADC) at multiple points (indexes) and perform DFE technology in parallel from multiple starting points, thereby requiring only the feedback time corresponding to the number of MUXs in each segment and thus alleviating the feedback time constraint compared to conventional DFE, so that the technology is suitable for high-speed operation. https://scholar.dgist.ac.kr/handle/20.500.11750/59182 https://scholar.dgist.ac.kr/handle/20.500.11750/58849 Title: 다중 칩 시스템을 위한 회로 장치 Author(s): 김가인 Abstract: 본 발명은 다중 칩 시스템을 위한 회로 장치에 관한 것으로, OFDM 방식으로 서로 인터페이스하는 복수의 칩을 포함하는 회로 장치에 있어서, 상기 복수의 칩 중 적어도 하나는, 디지털 데이터를 OFDM 방식으로 인코딩한 신호를 송신하는 OFDM 송신기를 포함하는 송신부, 상기 복수의 칩 중 적어도 다른 하나는 상기 송신한 신호를 수신하여 OFDM 방식으로 복조하여 디지털 데이터를 제공하는 OFDM 수신기를 포함하는 수신부를 포함하는 것을 특징으로 한다. https://scholar.dgist.ac.kr/handle/20.500.11750/58849 https://scholar.dgist.ac.kr/handle/20.500.11750/58535 Title: 디지털 decision feedback equalizer의 피드백 루프 완화 방법 및 장치 Author(s): 김가인; 김동건 https://scholar.dgist.ac.kr/handle/20.500.11750/58535