https://scholar.dgist.ac.kr/handle/20.500.11750/850 Sun, 05 Apr 2026 14:27:45 GMT 2026-04-05T14:27:45Z https://scholar.dgist.ac.kr/handle/20.500.11750/59306 Title: 메모리 인터리빙을 사용하는 계층 메모리 환경을 위한 동적 캐시 할당 방법 Author(s): 정진; 소진인; 이종건; 김대훈; 이환준 https://scholar.dgist.ac.kr/handle/20.500.11750/59306 https://scholar.dgist.ac.kr/handle/20.500.11750/59252 Title: 메모리 시스템 및 메모리 시스템의 동작 방법 Author(s): 김대훈; 이종건; 이환준; 김민호; 소진인; 박형원; 정진; 정예지; 장민우 Abstract: Memory systems and methods for operating the same. A memory system comprises a first memory, a second memory having an operating speed different from that of the first memory, a storage unit configured to store an instruction, a prefetcher configured to update prefetcher data in response to occurrence of cache hits and a processor configured to execute the instruction stored in the storage unit. When the instruction is executed, the processor is configured to generate prefetcher friendly data by filtering the prefetcher data, set a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory based on the prefetcher friendly data, and determine whether data of the first pointer area and the second pointer area are migrated, in consideration of a reference bit and the prefetcher friendly bit of the first and second pointer areas. https://scholar.dgist.ac.kr/handle/20.500.11750/59252 https://scholar.dgist.ac.kr/handle/20.500.11750/58750 Title: Processor, system, and method of operation for dynamic cache allocation Author(s): 이종건; 정진; 소진인; 이환준; 김대훈 Abstract: Processors, systems, and methods of operation are provided for dynamic cache allocation. The processor includes: a processing core configured to process each of a plurality of requests by accessing a respective one of a first memory and a second memory; a delay monitor configured to generate first delay information and second delay information, the first delay information including a first access delay to the first memory and the second delay information including a second access delay to the second memory; a plurality of cache lines, the plurality of cache lines being divided into a first partition and a second partition; and a decision engine configured to allocate each of the plurality of cache lines to one of the first partition and the second partition based on the first latency information and the second latency information. https://scholar.dgist.ac.kr/handle/20.500.11750/58750 https://scholar.dgist.ac.kr/handle/20.500.11750/58543 Title: 캐시 부채널 공격을 탐지하는 장치 및 방법 Author(s): 김대훈; 이환준; 박형원 Abstract: 본 발명의 바람직한 일 실시예로서, 하드웨어성능카운터는 공격 프로세스가 피공격 프로세스에 플러시 재적재 공격을 수행할 때 수집한 캐시미스의 수를 이용하여 1차적으로 부채널 공격 가능성을 판단하고, 이 후 공격프로세스가 단독으로 실행되는 경우에는 간섭이 줄어들어 캐시 미스율이 줄어들고, 다른 프로세스들과 동시에 실행되는 경우보다 캐시 미스율이 더 증가하는 특성을 이용하여 2차적으로 공격프로세스를 식별한다. https://scholar.dgist.ac.kr/handle/20.500.11750/58543