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Peregrine: A flexible hardware accelerator for LSTM with limited synaptic connection patterns

Title
Peregrine: A flexible hardware accelerator for LSTM with limited synaptic connection patterns
Authors
Kung, JaehaPark, JunkiPark, SehunKim, Jae-Joon
DGIST Authors
Kung, Jaeha
Issue Date
2019-06-06
Citation
Design Automation Conference
Type
Conference
ISBN
9781450367257
ISSN
0738-100X
Abstract
In this paper, we present an integrated solution to design a highperformance LSTM accelerator.We propose a fast and flexible hardware architecture, named Peregrine, supported by a stack of innovations from algorithm to hardware design. Peregrine first minimizes the memory footprint by limiting the synaptic connection patterns within the LSTM network. Also, Peregrine provides parallel Huffman decoders with adaptive clocking to provide flexibility in dealing with a wide range of sparsity levels in the weight matrices. All these features are incorporated in a novel hardware architecture to maximize energy-efficiency. As a result, Peregrine improves performance by ~38% and energy-efficiency by ~33% in speech recognition compared to the state-of-the-art LSTM accelerator. © 2019 Association for Computing Machinery.
URI
http://hdl.handle.net/20.500.11750/10106
DOI
10.1145/3316781.3317879
Publisher
Institute of Electrical and Electronics Engineers Inc.
Related Researcher
  • Author Kung, Jaeha Intelligent Digital Systems Lab
  • Research Interests 딥러닝, 가속하드웨어, 저전력 하드웨어, 고성능 시스템
Files:
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Collection:
Department of Information and Communication EngineeringIntelligent Digital Systems Lab2. Conference Papers


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