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dc.contributor.author Wang, Bo -
dc.contributor.author Nguyen, Truc Quynh -
dc.contributor.author Do, Anh Tuan -
dc.contributor.author Zhou, Jun -
dc.contributor.author Je, Min Kyu -
dc.contributor.author Kim, Tony Tae Hyoung -
dc.date.accessioned 2023-05-30T22:10:20Z -
dc.date.available 2023-05-30T22:10:20Z -
dc.date.created 2017-04-20 -
dc.date.issued 2015-02 -
dc.identifier.issn 1549-8328 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/45918 -
dc.description.abstract This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 μs. Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V∼0.6 V by the proposed CAM-assisted circuit. © 2014 IEEE. -
dc.language English -
dc.publisher Institute of Electrical and Electronics Engineers Inc. -
dc.title Design of an ultra-low voltage 9T SRAM with equalized bitline leakage and CAM-assisted energy efficiency improvement -
dc.type Article -
dc.identifier.doi 10.1109/TCSI.2014.2360760 -
dc.identifier.scopusid 2-s2.0-85027940188 -
dc.identifier.bibliographicCitation IEEE Transactions on Circuits and Systems I: Regular Papers, v.62, no.2, pp.441 - 448 -
dc.description.isOpenAccess FALSE -
dc.subject.keywordAuthor Bitline leakage equalization -
dc.subject.keywordAuthor content addressable memory -
dc.subject.keywordAuthor energy efficiency improvement -
dc.subject.keywordAuthor ultra-low voltage SRAM design -
dc.citation.endPage 448 -
dc.citation.number 2 -
dc.citation.startPage 441 -
dc.citation.title IEEE Transactions on Circuits and Systems I: Regular Papers -
dc.citation.volume 62 -
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Department of Electrical Engineering and Computer Science Information and Communication Engineering Research Center 1. Journal Articles

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