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dc.contributor.advisorLee, Jung Hyup-
dc.contributor.authorKim, Min Woo-
dc.contributor.other김민우-
dc.contributor.other이정협-
dc.contributor.other제민규-
dc.date.accessioned2017-05-10T08:53:18Z-
dc.date.available2017-01-18-
dc.date.issued2017-
dc.identifier.urihttp://dgist.dcollection.net/jsp/common/DcLoOrgPer.jsp?sItemId=000002324992en_US
dc.identifier.urihttp://hdl.handle.net/20.500.11750/1485-
dc.description.abstractThe recent researches are focus on the ultra-low power system like bio-medical device and IoT/IoE devices. In this case, the Wake-Up Receiver (WuRx) is absolutely necessary to make connections between devices with ultra-low power consumption. In the WuRx, the most important block is the Low-Noise Amplifier (LNA). The purpose of LNA in the WuRx is to ensure an accurate communication and reduce overall system power consumption between devices by performing several roles simultaneously on single stage like high gain and low noise and so on. This thesis presents the design of LNA for input stage of WuRx. For low power WuRx architecture, the differential output of tunable high gain, low noise figure, input/output isolation, differential output gain-phase balancing, good linearity, and low power are needed simultaneously. The pseudo-differential LNA incorporates an active single-to-differential conversion. By utilizing Q-enhancement circuit with LC tank at output nodes of pseudo-differential topology, the LNA has a tunable ultra-high gain. And, the both input/output isolation and differential output gain-phase balancing can be achieved by using capacitive cross-coupled technique. We described the bootstrapping capacitor for noise filtering effect in the pseudo-input stage. A 2.4GHz LNA design optimized in a 90nm CMOS process shows that the tolerable differential output gain-phase imbalances are up to 0.08dB and 0.1°, respectively. And, the simulation results show that proposed LNA achieves a noise figure of 4.7 to 5.7dB, and an IIP3 of -26.9dBm to -63.5dBm at the 2.4GHz according to the tunable current of Q-enhancement for obtaining variable gain of 26dB to 56dB with just 90 to 169μA current consumption, and 1V supply voltage. ⓒ 2017 DGIST-
dc.description.tableofcontentsⅠ. Introduction 1 -- Ⅱ. Design of single-to-differential LNA 5 -- 2.1 Impedance matching 5 -- 2.1.1 Basic matching networks for impedance matching 5 -- 2.1.2 Impedance matching using smith chart 9 -- 2.2 LNA topology-
dc.description.tableofcontentsPseudo-differential structure 11 -- 2.3 Size optimization of input transistor in LNA 13 -- 2.4 Q-enhancement technique 15 -- 2.4.1 Understanding of LC tank 15 -- 2.4.2 A negative resistance active circuit for canceling current leakage path 17 -- 2.5 Capacitive cross-coupling technique analysis 19 -- 2.5.1 The size decision of cascode transistor 20 -- 2.5.2 The concept of input/output isolation 23 -- 2.5.2.1 Qualitative interpretation of isolation 24 -- 2.5.2.2 Quantitative interpretation of isolation 25 -- 2.5.3 The intuitive concept of differential gain-phase balancing method 29 -- 2.6 Bootstrapping capacitor 31 -- 2.7 Gain analysis of LNA 35 -- 2.7.1 Gain analysis of pseudo-differential LNA with Q-enhancement 35 -- 2.7.2 Gain analysis of pseudo-differential LNA added CCC 37 -- 2.7.3 Gain analysis of pseudo-differential LNA bootstrapped 41 -- 2.8 Noise figure analysis of LNA 43 -- 2.8.1 The noise of input stage with parasitic capacitances 43 -- 2.8.2 The noise figure analysis of pseudo-differential LNA with Q-enhancement 49 -- 2.8.3 The noise figure analysis of pseudo-differential LNA added CCC 50 -- 2.8.4 The noise figure analysis of pseudo-differential LNA bootstrapped 53 -- 2.9 Output impedance analysis of LNA 54 -- Ⅲ. simulation result of LNA 58 -- 3.1 Size decision of M1 58 -- 3.2 Gain simulation 59 -- 3.3 NF simulation 61 -- 3.4 S11 simulation 63 -- 3.5 Single-to-differential conversion accuracy simulation 65 -- 3.6 Linearity simulation 67 -- 3.7 PVT variation simulation 69 -- 3.8 Consideration of design 72 -- Ⅳ. Conclusion 74-
dc.format.extent79-
dc.languageeng-
dc.publisherDGIST-
dc.subjectActive balun-
dc.subjectPseudo-differential LNA-
dc.subjectQ-enhancement-
dc.subjectCapacitive cross-coupling-
dc.subjectBootstrapping capacitor-
dc.subjectoutput gain-phase balancing-
dc.subjectinput/output isolation-
dc.subjectIC변압기-
dc.subjectPseudo-차동 저 잡음 증폭기-
dc.subjectQ강화회로-
dc.subjectBootstrapping 커패시터-
dc.subject출력 진폭-위상 조절-
dc.subject입력/출력 차폐-
dc.titleA Low-Power High-Gain Low Noise Amplifier For Wake-Up Receivers-
dc.title.alternativeWake-Up 수신기들을 위한 저전력, 고 증폭 저 잡음 증폭기 설계-
dc.typeThesis-
dc.identifier.doi10.22677/thesis.2324992-
dc.description.alternativeAbstract본 논문은 Wake-Up 수신기들을 위한 저 잡음 증폭기 설계의 내용을 담고 있다. 저전력 Wake-Up 수신기 구조를 위해서는 조절 가능한 차동 출력신호, 낮은 잡음, 입력/출력 차폐,차동 출력 진폭-위상 일치, 좋은 선형성 그리고 무엇보다도 저전의 저 잡음 증폭기가 필요해진다. Pseudo-차동 저잡음 증폭기 구조는 별도의 변압기없이 단일 입력 신호를 차동 출력 신호로 만들어 주는 역할을 한다. 그리고 pseudo-차동구조의 저 잡음 증폭기의 차동 출력단에 LC 공진회로와 Q를 강화시켜주는 회로의 조합을 활용함으로서 조절 가능한 고 이득 증폭기를 만들 수 있다. 뿐만 아니라, Capacitive cross-coupled구조를 저 잡음 증폭기의 cascode단에 적용하여 높은 입력/출력 차폐 능력과 차동 출력 진폭-위상 일치의 효과를 가져올 수 있다. 여기에, 전체적인 잡음을 줄이기 위하여 bootstrapping 커패시터를 pseudo 입력단에 병렬로 적용하여 신호 경로를 바꾸어 주었다. 이는 트랜지스터의 잡음을 걸러주는 역할을 하여 전체적인 잡음이 줄어드는 효과가 있다. 2.4GHz에서 90nm의 공정을 사용하여 차동출력 신호는 단지 0.08dB의 진폭차이와 0.1°의 위상차를 가진다. 그리고 1V의 전압을 사용하였고 Q를 강화시켜주는 회로에서 전류를 조절 함으로써 90에서 169μA의 가변적인 전류를 소모함과 동시에 이에 따라 4.7에서 5.7의 잡음 지수와 26에서 최대 56dB까지의 전압이득을 얻을 수 있게 된다. 그리고 선형성의 지수인 IIP3는 -26.9에서 -63.5까지로 다소 좋지 않지만 입력 신호의 전력에 따라 얼마든지 조절하여 낮출 수 있으므로 큰 문제가 되지 않는다. ⓒ 2017 DGIST-
dc.description.degreeMaster-
dc.contributor.departmentInformation and Communication Engineering-
dc.contributor.localauthorKim, Min Woo-
dc.contributor.localauthorLee, Jung Hyup-
dc.contributor.localauthorJe, Min Kyu-
dc.contributor.coadvisorJe, Min Kyu-
dc.date.awarded2017. 2-
dc.publisher.locationDaegu-
dc.description.databasedCollection-
dc.date.accepted2017-01-18-
dc.contributor.alternativeDepartment대학원 정보통신융합공학전공-


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