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An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing

Title
An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing
Author(s)
Liu, XinZhou, JunWang, ChaoChang, Kah-HyongLuo, JianwenLan, JingjingLiao, LeiLam, Yat-HeiYang, YongkuiWang, BoZhang, XinGoh, Wang LingKim, Tony Tae-HyoungJe, Minkyu
Issued Date
2015-12
Citation
IEEE Transactions on Circuits and Systems II: Express Briefs, v.62, no.12, pp.1149 - 1153
Type
Article
Author Keywords
Cognitivelow powersensor node processor (SNP)
Keywords
Co-Ordinate Rotation Digital ComputersCognitiveComputer HardwareDigital ComputersDigital Signal ProcessorsDiscrete Wavelet Packet TransformsEnergy EfficiencyEnergy UtilizationEnginesFast Fourier TransformsFinite Impulse Response FilteringHardwareImpulse ResponseInternet of Things (IOT)Low PowerMemory ArchitectureNeural NetworksPacket NetworksReconfigurable ArchitecturesReconfigurable HardwareReconfigurable MemorySensor Node Processor (SNP)Sensor NodesSignal ProcessingTiming CircuitsVehicle Speed Detection
ISSN
1549-7747
Abstract
An energy-efficient sensor node processor (SNP) is presented for intelligent sensing in Internet of Things (IoT) applications. To achieve ultralow energy consumption and satisfying performance, the proposed processor incorporates an ARM Cortex-M0 RISC core and diverse hardware accelerators, including discrete wavelet packet transform engine, finite-impulse-response filtering engine, fast Fourier transform engine, and coordinate rotation digital computer engine, to accelerate signal processing tasks. At the architecture level, dual-bus architecture with automatic bus sensing and reconfigurable memory access scheme are proposed. At the circuit level, digitally assisted cognitive sampling and ultralow-voltage operation with in situ timing-error monitoring techniques are employed. When applied to neural spike classification and vehicle speed detection, the proposed SNP consumes only 39 and 29 pJ/cycle, respectively. © 2015 IEEE.
URI
http://hdl.handle.net/20.500.11750/2573
DOI
10.1109/TCSII.2015.2468927
Publisher
Institute of Electrical and Electronics Engineers Inc.
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Department of Electrical Engineering and Computer Science Information and Communication Engineering Research Center 1. Journal Articles

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