Cited 6 time in webofscience Cited 4 time in scopus

An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing

Title
An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing
Authors
Liu, X[Liu, Xin]Zhou, J[Zhou, Jun]Wang, C[Wang, Chao]Chang, KH[Chang, Kah-Hyong]Luo, JW[Luo, Jianwen]Lan, JJ[Lan, Jingjing]Liao, L[Liao, Lei]Lam, YH[Lam, Yat-Hei]Yang, YK[Yang, Yongkui]Wang, B[Wang, Bo]Zhang, X[Zhang, Xin]Goh, WL[Goh, Wang Ling]Kim, TTH[Kim, Tony Tae-Hyoung]Je, MK[Je, Minkyu]
DGIST Authors
Je, MK[Je, Minkyu]
Issue Date
2015-12
Citation
IEEE Transactions on Circuits and Systems II: Express Briefs, 62(12), 1149-1153
Type
Article
Article Type
Article
Keywords
Co-Ordinate Rotation Digital ComputersCognitiveComputer HardwareDigital ComputersDigital Signal ProcessorsDiscrete Wavelet Packet TransformsEnergy EfficiencyEnergy UtilizationEnginesFast Fourier TransformsFinite Impulse Response FilteringHardwareImpulse ResponseInternet of Things (IOT)Low PowerMemory ArchitectureNeural NetworksPacket NetworksRe-Configurable ArchitecturesRe-Configurable HardwareRe-Configurable MemorySensor Node Processor (SNP)Sensor NodesSignal ProcessingTiming CircuitsVehicle Speed Detection
ISSN
1549-7747
Abstract
An energy-efficient sensor node processor (SNP) is presented for intelligent sensing in Internet of Things (IoT) applications. To achieve ultralow energy consumption and satisfying performance, the proposed processor incorporates an ARM Cortex-M0 RISC core and diverse hardware accelerators, including discrete wavelet packet transform engine, finite-impulse-response filtering engine, fast Fourier transform engine, and coordinate rotation digital computer engine, to accelerate signal processing tasks. At the architecture level, dual-bus architecture with automatic bus sensing and reconfigurable memory access scheme are proposed. At the circuit level, digitally assisted cognitive sampling and ultralow-voltage operation with in situ timing-error monitoring techniques are employed. When applied to neural spike classification and vehicle speed detection, the proposed SNP consumes only 39 and 29 pJ/cycle, respectively. © 2015 IEEE.
URI
http://hdl.handle.net/20.500.11750/2573
DOI
10.1109/TCSII.2015.2468927
Publisher
Institute of Electrical and Electronics Engineers Inc.
Files:
There are no files associated with this item.
Collection:
Information and Communication EngineeringETC1. Journal Articles


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