Cited 6 time in
Cited 4 time in
An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing
- An Ultralow-Voltage Sensor Node Processor With Diverse Hardware Acceleration and Cognitive Sampling for Intelligent Sensing
- Liu, X[Liu, Xin]; Zhou, J[Zhou, Jun]; Wang, C[Wang, Chao]; Chang, KH[Chang, Kah-Hyong]; Luo, JW[Luo, Jianwen]; Lan, JJ[Lan, Jingjing]; Liao, L[Liao, Lei]; Lam, YH[Lam, Yat-Hei]; Yang, YK[Yang, Yongkui]; Wang, B[Wang, Bo]; Zhang, X[Zhang, Xin]; Goh, WL[Goh, Wang Ling]; Kim, TTH[Kim, Tony Tae-Hyoung]; Je, MK[Je, Minkyu]
- DGIST Authors
- Je, MK[Je, Minkyu]
- Issue Date
- IEEE Transactions on Circuits and Systems II: Express Briefs, 62(12), 1149-1153
- Article Type
- Co-Ordinate Rotation Digital Computers; Cognitive; Computer Hardware; Digital Computers; Digital Signal Processors; Discrete Wavelet Packet Transforms; Energy Efficiency; Energy Utilization; Engines; Fast Fourier Transforms; Finite Impulse Response Filtering; Hardware; Impulse Response; Internet of Things (IOT); Low Power; Memory Architecture; Neural Networks; Packet Networks; Re-Configurable Architectures; Re-Configurable Hardware; Re-Configurable Memory; Sensor Node Processor (SNP); Sensor Nodes; Signal Processing; Timing Circuits; Vehicle Speed Detection
- An energy-efficient sensor node processor (SNP) is presented for intelligent sensing in Internet of Things (IoT) applications. To achieve ultralow energy consumption and satisfying performance, the proposed processor incorporates an ARM Cortex-M0 RISC core and diverse hardware accelerators, including discrete wavelet packet transform engine, finite-impulse-response filtering engine, fast Fourier transform engine, and coordinate rotation digital computer engine, to accelerate signal processing tasks. At the architecture level, dual-bus architecture with automatic bus sensing and reconfigurable memory access scheme are proposed. At the circuit level, digitally assisted cognitive sampling and ultralow-voltage operation with in situ timing-error monitoring techniques are employed. When applied to neural spike classification and vehicle speed detection, the proposed SNP consumes only 39 and 29 pJ/cycle, respectively. © 2015 IEEE.
- Institute of Electrical and Electronics Engineers Inc.
There are no files associated with this item.
- Information and Communication EngineeringETC1. Journal Articles
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.