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High Bandwidth Efficiency and Low Power Consumption Walsh Code Implementation Methods for Body Channel Communication
- High Bandwidth Efficiency and Low Power Consumption Walsh Code Implementation Methods for Body Channel Communication
- Ho, CK[Ho, Chee Keong]; Cheong, JH[Cheong, Jia Hao]; Lee, J[Lee, Junghyup]; Kulkarni, V[Kulkarni, Vishal]; Li, P[Li, Peng]; Liu, X[Liu, Xin]; Je, M[Je, Minkyu]
- DGIST Authors
- Je, M[Je, Minkyu]
- Issue Date
- IEEE Transactions on Microwave Theory and Techniques, 62(9), 1867-1878
- Article Type
- Bandwidth Efficiency; Body Channel Communications (BCC); Clocks; Cmos Integrated Circuits; Digital Transmission; Freons; Frequency-Selective Digital Transmission (FSDT); Harmonic Frequency; Human Body Communication; Human Body Communications; Low-Power Consumption; Power Consumption Reduction; Radio; Synchronization; Transmitters; Walsh Code; Wireless
- With the growing number of wearable devices and applications, there is an increasing need for a flexible body channel communication (BCC) system that supports both scalable data rate and low power operation. In this paper, a highly flexible frequency-selective digital transmission (FSDT) transmitter that supports both data scalability and low power operation with the aid of two novel implementation methods is presented. In an FSDT system, data rate is limited by the number of Walsh spreading codes available for use in the optimal body channel band of 40-80 MHz. The first method overcomes this limitation by applying multi-level baseband coding scheme to a carrierless FSDT system to enhance the bandwidth efficiency and to support a data rate of 60 Mb/s within a 40-MHz bandwidth. The proposed multi-level coded FSDT system achieves six times higher data rate as compared to other BCC systems. The second novel implementation method lies in the use of harmonic frequencies of a Walsh encoded FSDT system that allows the BCC system to operate in the optimal channel bandwidth between 40-80 MHz with half the clock frequency. Halving the clock frequency results in a power consumption reduction of 32%. The transmitter was fabricated in a 65-nm CMOS process. It occupies a core area of 0.24×, 0.3 mm2. When operating under a 60-Mb/s data-rate mode, the transmitter consumes 1.85 mW and it consumes only 1.26 mW when operating under a 5-Mb/s data-rate mode. © 2014 IEEE.
- Institute of Electrical and Electronics Engineers Inc.
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