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Issue Date	Title Author(s) Journal	View
2015-01	BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems Wang, Chao ; Zhou, Jun ; Weerasekera, Roshan ; Zhao, Bin ; Liu, Xin ; Royannez, Philippe ; Je, Minkyu IEEE Transactions on Circuits and Systems I: Regular Papers, v.62, no.1, pp.139 - 148, 2015-01	696

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