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BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems
  • Wang, Chao ; 
  • Zhou, Jun ; 
  • Weerasekera, Roshan ; 
  • Zhao, Bin ; 
  • Liu, Xin ; 
  • Royannez, Philippe ; 
  • Je, Minkyu
  • 2015-01
  • Wang, Chao. (2015-01). BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(1), 139–148. doi: 10.1109/TCSI.2014.2354752
  • Institute of Electrical and Electronics Engineers Inc.
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