A Triboelectric Energy-Harvesting Interface With Scalable Multi-Chip-Stacked Bias-Flip and Daisy-Chained Synchronous Signaling Techniques

Abstract

This article presents an energy-harvesting (EH) interface chip system for triboelectric nanogenerators (TENGs). Despite TENG's numerous advantages, its high open-circuit voltage and large parasitic capacitance (C-T) give a considerable burden to design TENG-EH integrated circuits (ICs). In this work, a scalable multi-chip-stacked bias-flip (MCS-BF) technique is proposed to harvest TENG energy with ultra-high extraction voltage, exceeding an LDMOS transistor's voltage-rating limit (similar to 70 V). Even in multi-chip-stacked structures, the MCS-BF utilizing a series inductor cancels the energy loss caused by C-T. Furthermore, a practical solution to synchronize chip-to-chip control signals without over-voltage stress is also presented, even when many chips are daisy-chained together. The proposed TENG-EH chips were fabricated in a 0.18-mu m BCD process. In experiments with a real wind-TENG, an extremely high extraction voltage of 130 V (195 V) was successfully demonstrated with two (three) MCS-BF chips. Also, a harvested power per TENG area was measured to be 96.4 mu W/cm(2) with a two-chip solution, which is 4x higher than previous state-of-the-art TENG-EH chips. The conversion from rectified input to regulated (battery voltage) output attained a measured peak efficiency of 70.7%. The proposed TENG-EH multi-chip system offers a 3.14x power extraction gain (figure of merit).