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A novel hardware architecture of intra-predictor generator for H.264/AVC Codec
- A novel hardware architecture of intra-predictor generator for H.264/AVC Codec
- Kwak, Sang Hoon; Kim, Jin Wook; Har, Dong Soo
- Issue Date
- IEICE Transactions on Information and Systems, E91-D(7), 2083-2086
- Article Type
- Article; Proceedings Paper
- Architectural Design; Architecture Level Optimization; Clock Cycles; Core Part; Dedicated Hardware; Gate Count; H.264/AVC; Hardware; Hardware Implementation; High Resolution; Intra Predictor; Motion Picture Experts Group Standards; Novel Architecture; Novel Hardware; Pixel Values; Real-Time Encoding; Video Recording
- The intra-prediction unit is an essential part of H.264 codec, since it reduces the amount of data to be encoded by predicting pixel values (luminance and chrominance) from their neighboring blocks. A dedicated hardware implementation for the intra-prediction unit is required for real-time encoding and decoding of high resolution video data. To develop a cost-effective intra-prediction unit this paper proposes a novel architecture of intra-predictor generator, the core part of intra-prediction unit. The proposed intra-predictor generator enables the intra-prediction unit to achieve significant clock cycle reduction with approximately the same gate count, as compared to Huang's work . Copyright © 2008 The Institute of Electronics, Information and Communication Engineers.
- Institute of Electronics, Information and Communication Engineers
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