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Cooperative Memory Deduplication with Intel® Data Streaming Accelerator
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dc.contributor.author Ji, Houxiang -
dc.contributor.author Kim, Minho -
dc.contributor.author Oh, Seonmu -
dc.contributor.author Kim, Daehoon -
dc.contributor.author Kim, Nam Sung -
dc.date.accessioned 2025-02-21T15:10:13Z -
dc.date.available 2025-02-21T15:10:13Z -
dc.date.created 2025-01-31 -
dc.date.issued 2025-01 -
dc.identifier.issn 1556-6056 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/57918 -
dc.description.abstract Memory deduplication plays a critical role in reducing memory consumption and the total cost of ownership (TCO) in hyperscalers, particularly as the advent of large language models imposes unprecedented demands on memory resources. However, conventional CPU-based memory deduplication can interfere with co-running applications, significantly impacting the performance of time-sensitive workloads. Intel introduced the on-chip Data Streaming Accelerator (DSA), providing high-performance data movement and transformation capabilities, including comparison and checksum calculation, which are heavily utilized in the deduplication. In this work, we enhance a widely-used kernel-space memory deduplication feature, Kernel Samepage Merging (ksm ), by selectively offloading these operations to the DSA. Our evaluation demonstrates that CPU-based ksm can lead to 5.0-10.9× increase in the tail latency of co-running applications while DSA-based ksm limits the latency increase to just 1.6× while achieving comparable memory savings. © IEEE. -
dc.language English -
dc.publisher Institute of Electrical and Electronics Engineers -
dc.title Cooperative Memory Deduplication with Intel® Data Streaming Accelerator -
dc.type Article -
dc.identifier.doi 10.1109/LCA.2025.3527458 -
dc.identifier.wosid 001414752800001 -
dc.identifier.scopusid 2-s2.0-85214705640 -
dc.identifier.bibliographicCitation Ji, Houxiang. (2025-01). Cooperative Memory Deduplication with Intel® Data Streaming Accelerator. IEEE Computer Architecture Letters, 24(1), 29–32. doi: 10.1109/LCA.2025.3527458 -
dc.description.isOpenAccess FALSE -
dc.subject.keywordAuthor Memory deduplication -
dc.subject.keywordAuthor hardware accelerator -
dc.subject.keywordAuthor operating system -
dc.citation.endPage 32 -
dc.citation.number 1 -
dc.citation.startPage 29 -
dc.citation.title IEEE Computer Architecture Letters -
dc.citation.volume 24 -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.relation.journalResearchArea Computer Science -
dc.relation.journalWebOfScienceCategory Computer Science, Hardware & Architecture -
dc.type.docType Article -
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