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Defect-mediated enhancement of memory window in IGZO-channel ferroelectric field effect transistors
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| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yang, Hyojin | - |
| dc.contributor.author | Kim, Haesung | - |
| dc.contributor.author | Kim, Hwan Jin | - |
| dc.contributor.author | Kim, Dong Myong | - |
| dc.contributor.author | Choi, Sung-Jin | - |
| dc.contributor.author | Kim, Dae Hwan | - |
| dc.contributor.author | Lee, Yoon Jung | - |
| dc.contributor.author | Bae, Jong-Ho | - |
| dc.date.accessioned | 2026-01-21T22:10:14Z | - |
| dc.date.available | 2026-01-21T22:10:14Z | - |
| dc.date.created | 2025-12-04 | - |
| dc.date.issued | 2026-03 | - |
| dc.identifier.issn | 1369-8001 | - |
| dc.identifier.uri | https://scholar.dgist.ac.kr/handle/20.500.11750/59406 | - |
| dc.description.abstract | Ferroelectric HfZrO2 (HZO) FETs with amorphous InGaZnO (IGZO) channels promise low-power, back-end-of-line memories, yet their memory window (MW) is often limited by poor hole supply. We show that simply advancing rapid thermal annealing (RTA) from post channel to post HZO deposition doubles the MW without additional layers or dopants. Devices annealed immediately after HZO deposition exhibit a 2.3 V MW, whereas those annealed after IGZO sputtering remain below 1 V. Depth-profiling X-ray photoelectron spectroscopy reveals a pronounced oxygen vacancy (Vo) peak at the HZO/IGZO interface only in early-annealed samples. Positively charged Vos provide the compensating charges required for full ferroelectric switching under negative gate bias, overcoming the intrinsic hole deficiency of IGZO. This defect engineering strategy enhances ferroelectric switching within a simple metal-ferroelectric-semiconductor stack, offering a scalable, process-compatible path toward high-density oxide channel FeFETs. | - |
| dc.language | English | - |
| dc.publisher | Elsevier | - |
| dc.title | Defect-mediated enhancement of memory window in IGZO-channel ferroelectric field effect transistors | - |
| dc.type | Article | - |
| dc.identifier.doi | 10.1016/j.mssp.2025.110268 | - |
| dc.identifier.wosid | 001630189400002 | - |
| dc.identifier.scopusid | 2-s2.0-105022459725 | - |
| dc.identifier.bibliographicCitation | Materials Science in Semiconductor Processing, v.204 | - |
| dc.description.isOpenAccess | FALSE | - |
| dc.citation.title | Materials Science in Semiconductor Processing | - |
| dc.citation.volume | 204 | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
| dc.relation.journalResearchArea | Engineering; Materials Science; Physics | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic; Materials Science, Multidisciplinary; Physics, Applied; Physics, Condensed Matter | - |
| dc.type.docType | Article | - |
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