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Beyond Page Migration: Enhancing Tiered Memory Performance via Integrated Last-Level Cache Management and Page Migration

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dc.contributor.author Lee, Hwanjun -
dc.contributor.author Kim, Minho -
dc.contributor.author Jung, Yeji -
dc.contributor.author Oh, Seonmu -
dc.contributor.author Kang, Ki-Dong -
dc.contributor.author Lee, Seunghak -
dc.contributor.author Kim, Daehoon -
dc.date.accessioned 2026-02-04T21:10:12Z -
dc.date.available 2026-02-04T21:10:12Z -
dc.date.created 2025-11-20 -
dc.date.issued 2025-10-22 -
dc.identifier.isbn 9798400715730 -
dc.identifier.issn 1072-4451 -
dc.identifier.uri https://scholar.dgist.ac.kr/handle/20.500.11750/59903 -
dc.description.abstract Emerging memory interconnect technologies, such as Compute Express Link (CXL), enable scalable memory expansion by integrating heterogeneous memory components like local DRAM and CXL-attached DRAM. These tiered memory systems offer potential benefits in bandwidth and capacity, but their heterogeneous performance characteristics pose significant challenges for efficient memory management. Traditional approaches, including hotness-based page placement, prioritize latency reduction by retaining frequently accessed data in near memory. However, these methods often fail to utilize aggregate memory bandwidth effectively, leading to imbalanced traffic and performance degradation under memory-heavy workloads. Additionally, the reliance on costly page migrations introduces overheads that impede responsiveness to workload variations. To address these challenges, we propose TierTune, a dynamic memory management framework integrating Last-Level Cache (LLC) partitioning and page migration. TierTune dynamically partitions the LLC between near and far memory nodes, rapidly mitigating latency imbalances and balancing memory traffic more effectively than software-based page migration. We extend this approach with a migration policy that dynamically redistributes pages to address persistent imbalances, incorporating cache hierarchy effects and bandwidth pressure into placement decisions. Experimental evaluations demonstrate that TierTune improves performance by 19.6% on average compared to state-of-the-art page migration policies across diverse workloads by balancing memory traffic more effectively and reducing migration overheads. © 2025 Elsevier B.V., All rights reserved. -
dc.language English -
dc.publisher IEEE Computer Society -
dc.relation.ispartof MICRO '25: Proceedings of the 58th IEEE/ACM International Symposium on Microarchitecture -
dc.title Beyond Page Migration: Enhancing Tiered Memory Performance via Integrated Last-Level Cache Management and Page Migration -
dc.type Conference Paper -
dc.identifier.doi 10.1145/3725843.3756063 -
dc.identifier.wosid 001609964400116 -
dc.identifier.scopusid 2-s2.0-105021380503 -
dc.identifier.bibliographicCitation IEEE/ACM International Symposium on Microarchitecture, pp.1763 - 1776 -
dc.identifier.url https://www.microarch.org/micro58/program/ -
dc.citation.conferenceDate 2025-10-18 -
dc.citation.conferencePlace KO -
dc.citation.conferencePlace 서울 -
dc.citation.endPage 1776 -
dc.citation.startPage 1763 -
dc.citation.title IEEE/ACM International Symposium on Microarchitecture -
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