Unveiling charge trapping dynamics in SiO2/HfZrOX-based ferroelectric field-effect-transistors to minimize read-after-write latency

Abstract

Read-after-write latency (RWL) is a major limitation of hafnium zirconium oxide (HZO)-based ferroelectric fieldeffect transistors (FeFETs) for non-volatile memory and in-memory computing. We investigate RWL in HZO metal-ferroelectric-insulator-semiconductor (MFIS) FeFETs with a SiO2 interfacial layer by combining transient measurements in the write-0 (W0) state with a physics-based current model that captures polarization and charge de/trapping. RWL shows a strong dependence on charge-trapping dynamics, with extracted activation energies of 6.6-43.2 meV, indicating tunneling, hopping, and phonon-assisted tunneling as the dominant mechanisms over different pulse-width regimes. We further demonstrate a trade-off between RWL reduction and memory-window retention imposed by the de-trapping time. These results show that engineering the interlayer-Si interface to suppress trap states is more effective for mitigating RWL than operating-temperature tuning and provide design guidelines for high-speed, low-power FeFET memories.