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BlockPIM: Enabling Sparse LLM Inference on Dense PIM Architectures

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dc.contributor.author Kim, Seulki -
dc.contributor.author Jang, Yewon -
dc.contributor.author Jeon, Yunhyeong -
dc.contributor.author Ryu, Kyeonghyeon -
dc.contributor.author Kim, Daehoon -
dc.date.accessioned 2026-10-23T14:10:17Z -
dc.date.available 2026-10-23T14:10:17Z -
dc.date.created 2026-08-07 -
dc.date.issued 2026-07 -
dc.identifier.issn 1556-6056 -
dc.identifier.uri https://scholar.dgist.ac.kr/handle/20.500.11750/61019 -
dc.description.abstract Large Language Models (LLMs) have intensified the memory wall during inference, where performance is increasingly limited by memory bandwidth rather than computation. While Processing-In-Memory (PIM) and model compression techniques mitigate this issue, existing sparse PIM designs rely on CSR/COO formats that assume ultra-high sparsity (e.g., >90%), which is difficult to achieve in practical LLMs without significant accuracy loss. Moreover, fine-grained indexing introduces substantial metadata overhead, diminishing the benefits of pruning, especially under low-bit quantization. To address this mismatch, we propose BlockPIM, a PIM architecture that employs hardware-aligned coarse-grained pruning to efficiently execute sparse LLMs on standard dense computation units. BlockPIM replaces per-element indices with compact bitmaps and contiguous non-zero blocks, enabling sparse workloads to be processed directly on dense execution pipelines without complex index decoding or irregular control flow. Experimental results show that BlockPIM achieves up to 8.0 & times; and 3.6 & times; speedups over the NPU and state-of-the-art sparse PIM baselines, respectively, while reducing energy consumption by up to 95.2% and providing superior memory efficiency under practical accuracy constraints. -
dc.language English -
dc.publisher IEEE COMPUTER SOC -
dc.title BlockPIM: Enabling Sparse LLM Inference on Dense PIM Architectures -
dc.type Article -
dc.identifier.doi 10.1109/LCA.2026.3715204 -
dc.identifier.wosid 001860452500001 -
dc.identifier.scopusid 2-s2.0-105045803416 -
dc.identifier.bibliographicCitation IEEE COMPUTER ARCHITECTURE LETTERS, v.25, no.2, pp.311 - 314 -
dc.description.isOpenAccess FALSE -
dc.subject.keywordAuthor Architecture -
dc.subject.keywordAuthor DRAM chips -
dc.subject.keywordAuthor Hardware -
dc.subject.keywordAuthor Quantization (signal) -
dc.subject.keywordAuthor Indexes -
dc.subject.keywordAuthor Modeling -
dc.subject.keywordAuthor Computer architecture -
dc.subject.keywordAuthor Memory -
dc.subject.keywordAuthor Metadata -
dc.subject.keywordAuthor Indexing -
dc.subject.keywordAuthor Processing-in-memor -
dc.subject.keywordAuthor ylarge language models -
dc.subject.keywordAuthor sparse inference -
dc.subject.keywordAuthor model compression -
dc.citation.endPage 314 -
dc.citation.number 2 -
dc.citation.startPage 311 -
dc.citation.title IEEE COMPUTER ARCHITECTURE LETTERS -
dc.citation.volume 25 -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.relation.journalResearchArea Computer Science -
dc.relation.journalWebOfScienceCategory Computer Science, Hardware & Architecture -
dc.type.docType Article -
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