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Article
A Timing Relaxed Pre-Decision Feedforward Equalizer for DSP-Based Wireline Receiver Using Hardware-in-the-Loop Verification on FPGA
  • Lee, Jae-Geon ; 
  • Ok, Sang-Hyeon ; 
  • Kwon, Joon-Seok ; 
  • Lee, Kwang-Ho ; 
  • Ju, Haram ; 
  • Jeong, Gyu-Seob ; 
  • Bae, Woorham ; 
  • Kim, Gain ; 
  • Park, Kwanseo ; 
  • Choo, Min-Seong
  • 2026-11
  • IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.73, no.11, pp.7597 - 7609
  • IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
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