김가인
Kim, GainDepartment of Electrical Engineering and Computer Science
학력
- 2015 ~ 2018로잔 연방 공과대학교 박사
- 2013 ~ 2015로잔 연방 공과대학교 석사
- 2010 ~ 2013로잔 연방 공과대학교 학사
경력
- 2020 ~ 2022삼성전자
- 2018 ~ 2020KAIST 정보전자연구소 / 연수연구원
- 2016 ~ 2018IBM Zurich Research Laboratory / Contractor
수상실적
- 2018 2018 IEEE Circuits and Systems Pre-Doctoral Scholarship / Institute of Electrical and Electronics Engineers
- 2017 IEEE CASS Scholarship (2017) / Institute of Electrical and Electronics Engineers
연구실 소개
- Circuits And Systems for Signal Processing Laboratory
-
The mission of the Circuits and Systems for Signal Processing (CASSP) laboratory is to develop energy-efficient high-performance signal and data processing accelerator systems for connected electronic devices, by exploring design opportunities that come from the relationships among the characteristics of the signal- and data-to-be-processed, analog & mixed-signal circuits, and digital signal processing & accelerator systems.
Research Interests
Related Keyword
- "A 112-Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Interleaved Time-Based ADC in 5-nm FinFET", IEEE Journal of Solid-State Circuits, v.61, no.1, pp.8 - 19
- "An 86.71875-GHz RF Transceiver for 57.8125-Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28-nm CMOS", IEEE Journal of Solid-State Circuits, v.60, no.11, pp.4242 - 4251
- "A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform", Lee, Jaewon. (2025-06). A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 33(6), 1570–1581. doi: 10.1109/TVLSI.2025.3553400
- "An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses", Choi, Won Joon. (2025-05). An On-Chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 33(5), 1432–1436. doi: 10.1109/TVLSI.2024.3497213
- "BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics", Lee, Jaehyun. (2025-03). BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. IEEE Journal of Solid-State Circuits, 60(3), 963–976. doi: 10.1109/JSSC.2024.3505960
- "A 144 mW 76 Gb/s DAC-Based Discrete Multitone Wireline Transmitter in 5nm FinFET", 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025, pp.109 - 112
- "A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET", International Solid-State Circuits Conference, pp.144 - 146
- "A Time-Domain Analysis, Modeling and Optimization of Analog Amplitude-Modulated Multi-Tone Serial Data Transceivers", Kim, Donggeon. (2025-01-21). A Time-Domain Analysis, Modeling and Optimization of Analog Amplitude-Modulated Multi-Tone Serial Data Transceivers. 24th International Conference on Electronics, Information, and Communication, ICEIC 2025, 1–6. doi: 10.1109/ICEIC64972.2025.10879655
- "A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links", Jang, Seoyoung. (2024-08-21). A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links. 21st International System-on-Chip Design Conference, ISOCC 2024, 432–433. doi: 10.1109/ISOCC62682.2024.10762411
- "A Discrete Multitone Wireline Transceiver Using Optimal Loading Over Reflective Channel For ADC-Based High-Speed Serial Links", Lee, Jaewon. (2024-08-20). A Discrete Multitone Wireline Transceiver Using Optimal Loading Over Reflective Channel For ADC-Based High-Speed Serial Links. 21st International System-on-Chip Design Conference, ISOCC 2024, 35–36. doi: 10.1109/ISOCC62682.2024.10762670
연구분야
미래유망 신기술(6T)
국가과학기술표준분류