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Department of Electrical Engineering and Computer Science
Circuits And Systems for Signal Processing Laboratory
1. Journal Articles
BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics
Lee, Jaehyun
;
Choi, Dong-Gu
;
Kim, Gain
;
Song, Minyoung
;
Yoon, Jong-Hyeok
Department of Electrical Engineering and Computer Science
Wireless Integrated Systems Engineering Lab.
1. Journal Articles
Department of Electrical Engineering and Computer Science
Intelligent Integrated Circuits and Systems Lab
1. Journal Articles
Department of Electrical Engineering and Computer Science
Circuits And Systems for Signal Processing Laboratory
1. Journal Articles
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Title
BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics
Issued Date
2025-03
Citation
Lee, Jaehyun. (2025-03). BEE-SLAM: A 65-nm 17.96-TOPS/W Location-Sharing-Based Multi-Agent Neuromorphic SLAM Accelerator for Swarm Robotics. IEEE Journal of Solid-State Circuits, 60(3), 963–976. doi: 10.1109/JSSC.2024.3505960
Type
Article
Author Keywords
Bee communication
;
location sharing
;
neuromorphic system
;
simultaneous localization and mapping (SLAM)
;
swarm robotics
ISSN
0018-9200
Abstract
Multi-agent (MA) simultaneous localization and mapping (SLAM) has been rigorously explored to enhance map accuracy in swarm robotics. Although centralized MA SLAM systems, which depend on a server for complex computations in map optimization, have been extensively studied, the circuit-domain approaches to decentralized MA SLAM systems are still limited due to challenges such as limited memory capacity and security vulnerabilities in wireless inter-agent data transmission. Thus, we propose a BEE-SLAM accelerator, a location-sharing MA neuromorphic SLAM accelerator inspired by bee communication for decentralized MA SLAM systems. The location-sharing-based MA error correction (MAEC) is employed to attain accurate map results without loop closure with a 94.81% reduced number of operations compared to the global map-based MA SLAM. In addition, a 7 × 7 pulsewidth modulation (PWM)-based hybrid mixed-signal/digital pose-cell (HY-PC) array with pseudo pose cells (PPCs) achieves 2.04 × energy efficiency compared to the oscillatory pose-cell array. The test chip fabricated in a 65-nm CMOS technology achieves a peak energy efficiency of 17.96 TOPS/W under 350 × 450 m outdoor exploration. © IEEE.
URI
http://hdl.handle.net/20.500.11750/57467
DOI
10.1109/JSSC.2024.3505960
Publisher
Institute of Electrical and Electronics Engineers
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