BIT ERROR CORRECTION APPARATUS FOR HIGH-SPEED WIRED INTERFACE

Abstract

A bit error correction apparatus for a high-speed wired interface, according to some embodiments, comprises: an FFE circuit that receives a digitized bit stream and generates an FFE output value; a decision circuit that generates a decision output value by performing a decision operation on the FFE output value; a reconfigured FFE circuit that generates a reconfigured FFE output value by performing FFE on the decision output value; a summer that calculates a difference value between the reconfigured FFE output value and the FFE output value; a comparator that determines whether or not an error has occurred in the bit stream, by comparing the difference value with a threshold value; and an error corrector that performs error correction on the bit stream, when it is determined that the error has occurred in the bit stream as a result of the determination performed by the comparator.