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Department of Electrical Engineering and Computer Science
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Master
Aggressive Interrupt Throttling for low latency in Data Center Servers
Park Hyungwon
Department of Electrical Engineering and Computer Science
Theses
Master
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WEB OF SCIENCE
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SCOPUS
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Title
Aggressive Interrupt Throttling for low latency in Data Center Servers
Alternative Title
데이터 센터 서버의 지연 시간을 줄이기위한 적극적인 인터럽트 조절
DGIST Authors
Kim, Daehoon
;
Park, Hyungwon
;
Lee, Sungjin
Advisor
김대훈
Co-Advisor(s)
Sungjin Lee
Issued Date
2019
Awarded Date
2019-02
Citation
Park Hyungwon. (2019). Aggressive Interrupt Throttling for low latency in Data Center Servers. doi: 10.22686/thesis.200000171477
Type
Thesis
Table Of Contents
Ⅰ. Introduction ·························································································1
II. Background and Motivation
2.1 Interrupt Throttling ··········································································3
2.2 Current Interrupt Throttling·································································3
2.3 Limitation of Current Intel Dynamic Interrupt Throttling ······························5
2.4 Limitation of static throttling·······························································8
III. Turbo Throttle of Network interrupts
3.1 The Overall Architecture····································································9
3.2 Discussion··················································································· 13
IV. Evaluation
4.1 Experiment Environment ································································· 14
4.2 Adaptive Throttle Level Change ························································· 15
4.3 Tail Latency ················································································ 17
4.3.1 High load··············································································· 17
4.3.2 Low load ··············································································· 18
V. Related Work
5.1 DVFS for Tail latency····································································· 19
5.2 Cache Partitioning for Tail latency ······················································ 19
VI. Conclusion and Future Work
6.1 Conclusion ·················································································· 20
6.2 Future work ················································································· 20
URI
http://dgist.dcollection.net/common/orgView/200000171477
http://hdl.handle.net/20.500.11750/10733
DOI
10.22686/thesis.200000171477
Degree
MASTER
Department
Information and Communication Engineering
Publisher
DGIST
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