Full metadata record
DC Field | Value | Language |
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dc.contributor.author | Im, Junsu | - |
dc.contributor.author | Kim, Hanbyeol | - |
dc.contributor.author | Won, Yumin | - |
dc.contributor.author | Oh, Jiho | - |
dc.contributor.author | Kim, Minjae | - |
dc.contributor.author | Lee, Sungjin | - |
dc.date.accessioned | 2021-01-22T06:59:41Z | - |
dc.date.available | 2021-01-22T06:59:41Z | - |
dc.date.created | 2020-07-17 | - |
dc.date.issued | 2020-07 | - |
dc.identifier.issn | 1556-6056 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11750/12655 | - |
dc.description.abstract | Thanks to the advance of NAND scaling technologies, an ultra-scale SSD (e.g., >> 100 TB) is introduced to markets. This rapid increase of SSD capacity, however, comes at the cost of more DRAM which resides in an SSD controller for logical-to-physical (L2P) address translation. Many have proposed various address translation algorithms to reduce DRAM, but they fail to provide short read latency, in particular when a workload has weak locality. This letter proposes a novel probability-based address translation algorithm, called ProbFTL. In contrast to existing translation techniques that maintain exact L2P mapping, ProbFTL employs a probability-based data structure, a bloom filter, for address translation. By leveraging a space-efficient nature of a bloom filter, ProbFTL reduces the amount of DRAM for address translation to 20 percent of the existing techniques. The read latency of ProbFTL is not affected from locality of a workload; ProbFTL guarantees a read amplification factor of 1.1 even under a random read workload. ProbFTL exhibits slightly worse garbage collection efficiency, but its write amplification factor is maintained sufficiently low. | - |
dc.language | English | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.title | Probability-based Address Translation for Flash SSDs | - |
dc.type | Article | - |
dc.identifier.doi | 10.1109/LCA.2020.3006529 | - |
dc.identifier.scopusid | 2-s2.0-85087502706 | - |
dc.identifier.bibliographicCitation | IEEE Computer Architecture Letters, v.19, no.2, pp.97 - 100 | - |
dc.description.isOpenAccess | FALSE | - |
dc.subject.keywordAuthor | Address Translation | - |
dc.subject.keywordAuthor | Bloom Filters | - |
dc.subject.keywordAuthor | Hardware Acceleration | - |
dc.subject.keywordAuthor | Solid-state Drives | - |
dc.subject.keywordPlus | Data structures | - |
dc.subject.keywordPlus | Flash-based SSDs | - |
dc.subject.keywordPlus | Address translation | - |
dc.subject.keywordPlus | Garbage collection | - |
dc.subject.keywordPlus | Read amplifications | - |
dc.subject.keywordPlus | Read latencies | - |
dc.subject.keywordPlus | Scaling technology | - |
dc.subject.keywordPlus | Space efficient | - |
dc.subject.keywordPlus | Weak locality | - |
dc.subject.keywordPlus | Write amplifications | - |
dc.subject.keywordPlus | Probability | - |
dc.citation.endPage | 100 | - |
dc.citation.number | 2 | - |
dc.citation.startPage | 97 | - |
dc.citation.title | IEEE Computer Architecture Letters | - |
dc.citation.volume | 19 | - |
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