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Low voltage operation of GaN vertical nanowire MOSFET

Title
Low voltage operation of GaN vertical nanowire MOSFET
Author(s)
Son, Dong HyeokJo, Young WooSeo, Jae HwaWon, Chul HoIm, Ki SikLee, Yong SooJang, Hwan SooKim, Dae HyunKang, In ManLee, Jung Hee
Issued Date
2018-07
Citation
Solid-State Electronics, v.145, pp.1 - 7
Type
Article
Keywords
PERFORMANCESILICONCHANNEL
ISSN
0038-1101
Abstract
GaN gate-all-around (GAA) vertical nanowire MOSFET (VNWMOSFET) with channel length of 300 nm and diameter of 120 nm, the narrowest GaN-based vertical nanowire transistor ever achieved from the top-down approach, was fabricated by utilizing anisotropic side-wall wet etching in TMAH solution and photoresist etch-back process. The VNWMOSFET exhibited output characteristics with very low saturation drain voltage of less than 0.5 V, which is hardly observed from the wide bandgap-based devices. Simulation results indicated that the narrow diameter of the VNWMOSFET with relatively short channel length is responsible for the low voltage operation. The VNWMOSFET also demonstrated normally-off mode with threshold voltage (VTH) of 0.7 V, extremely low leakage current of ∼10−14 A, low drain-induced barrier lowering (DIBL) of 125 mV/V, and subthreshold swing (SS) of 66–122 mV/decade. The GaN GAA VNWMOSFET with narrow channel diameter investigated in this work would be promising for new low voltage logic application. © 2018 Elsevier Ltd
URI
http://hdl.handle.net/20.500.11750/13180
DOI
10.1016/j.sse.2018.03.001
Publisher
Elsevier Ltd
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