A digital converter and a controlling method are disclosed. The digital converter includes a sensing oscillator including a plurality of tri-state buffers configured to generate a sensing clock period signal corresponding to a change value of at least one of a resistive sensor and a capacitive sensor, a reference oscillator configured to generate a predetermined fixed clock period signal, a processor configured to change a connection state of the plurality of tri-state buffers, a frequency divider configured to scale up the generated sensing clock period signal based on a predetermined value; and a counter configured to count the scaled up sensing clock period signal based on the generated fixed clock cycle signal and output a counted digital value.
