Neural recording is an indispensable function required for the brain machine interface (BMI) and neuroscience research. In order to obtain high-quality neural signals with minimal noise, a low-noise performance needs to be provided by a front-end amplifier used for neural recording. At the same time, a lowpower operation must be achieved to avoid tissue damage. This paper presents the neural recording amplifier design optimized to achieve highest possible signal-to-noise ratio (SNR) based on advanced noise modeling which takes into account the effect of a finite source impedance determined by the characteristics of the tissue-electrode interface. The research on the finite source impedance was performed through animal experiments by using rats. The commercial products of NeuroNexus Technologies were implanted over the sensorimotor cortex. Then, the impedances were daily checked for 21 days by using TDT (Tucker-Davis Technologies) system. The front-end amplifier was designed for neural recording over the frequency range from 1 Hz to 10 kHz. The amplifier was implemented with TSMC 0.18-μm CMOS process. We also introduce the systematic procedure for optimizing the neural recording amplifier under the constraint of given power budget, while considering various electrode site areas and the change of the source impedance value over time. ⓒ 2016 DGIST
Table Of Contents
I. INTRODUCTION 1-- 1.1 Trend on the Brain Machine Interface and Neuroscience Research 1-- 1.2 Developed Neural Systems 8-- 1.3 Research Goal 11-- 1.4 Thesis Organization 13-- -- II. TISSUE-ELECTRODE INTERFACE 14-- 2.1 Materials and Methods 14-- 2.1.1 Animals 14-- 2.1.2 Surgical Procedures 16-- 2.1.3 Impedance Measurements 18-- 2.2 Measurements of the Source Impedance & Neural Signals 19-- 2.3 Modeling of the Source Impedance 26-- 2.4 Source Capacitance of the Commercial Products 31-- 2.5 Summary 37-- -- III. NOISE MODELING FOR NEURAL RECORDING AMPLIFIER 38-- 3.1 Simplified Circuit Model for Noise Modeling 38-- 3.2 Noise Contribution depending on the Source Impedance 40-- 3.2.1 Voltage Component 43-- 3.2.2 Correlation Component 43-- 3.2.3 Current Component 44-- 3.3 Noise Modeling without the Source Impedance 45-- 3.3.1 Optimization with Thermal Noise 46-- 3.3.2 Optimization with Thermal & Flicker Noises 52-- 3.3.3 Optimization with Power Budget & Signal Bandwidth 57-- 3.4 Noise Modeling with the Source Impedance 59-- 3.4.1 Analysis of Signal-to-Noise Ratio 59-- 3.4.2 Optimization given Source Impedance 62-- 3.4.3 Optimization with Chip Area 66-- 3.5 Summary 67-- -- IV. DESIGN OF NEURAL RECORDING AMPLIFIER 69-- 4.1 Topology of Neural Recording Amplifier 69-- 4.2 Biasing Circuit 71-- 4.3 Optimization in Signal-to-Noise Ratio 72-- 4.4 Optimization in the Power Budget 80-- 4.5 Optimization in the Chip Area 87-- -- V. SIMULATION RESULTS 90-- -- VI. CONCLUSION AND FUTURE WORK 94-- 6.1 Conclusion 94-- 6.2 Future Work 95-- -- References 96