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LightNorm: Area and Energy-Efficient Batch Normalization Hardware for On-Device DNN Training

Title
LightNorm: Area and Energy-Efficient Batch Normalization Hardware for On-Device DNN Training
Author(s)
Noh, Seock-HwanPark, JunsangPark, DahoonKoo, JahyunChoi, JeikKung, Jaeha
Issued Date
2022-10-25
Citation
IEEE International Conference on Computer Design, pp.443 - 450
Type
Conference Paper
ISBN
9781665461863
ISSN
2576-6996
Abstract
When training early-stage deep neural networks (DNNs), generating intermediate features via convolution or linear layers occupied most of the execution time. Accordingly, extensive research has been done to reduce the computational burden of the convolution or linear layers. In recent mobile-friendly DNNs, however, the relative number of operations involved in processing these layers has significantly reduced. As a result, the proportion of the execution time of other layers, such as batch normalization layers, has increased. Thus, in this work, we conduct a detailed analysis of the batch normalization layer to efficiently reduce the runtime overhead in the batch normalization process. Backed up by the thorough analysis, we present an extremely efficient batch normalization, named LightNorm, and its associated hardware module. In more detail, we fuse three approximation techniques that are i) low bit-precision, ii) range batch normalization, and iii) block floating point. All these approximate techniques are carefully utilized not only to maintain the statistics of intermediate feature maps, but also to minimize the off-chip memory accesses. By using the proposed LightNorm hardware, we can achieve significant area and energy savings during the DNN training without hurting the training accuracy. This makes the proposed hardware a great candidate for the on-device training. © 2022 IEEE.
URI
http://hdl.handle.net/20.500.11750/46793
DOI
10.1109/ICCD56317.2022.00072
Publisher
IEEE Computer Society
Related Researcher
  • 궁재하 Kung, Jaeha
  • Research Interests 딥러닝; 가속하드웨어; 저전력 하드웨어; 고성능 시스템
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Department of Electrical Engineering and Computer Science Intelligent Digital Systems Lab 2. Conference Papers

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