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dc.contributor.author Yang, Shao-Peng -
dc.contributor.author Kim, Minjae -
dc.contributor.author Nam, Sanghyun -
dc.contributor.author Park, Juhyung -
dc.contributor.author Choi, Jin-Yong -
dc.contributor.author Nam, Eyee Hyun -
dc.contributor.author Lee, Eunji -
dc.contributor.author Lee, Sungjin -
dc.contributor.author Kim, Bryan S. -
dc.date.accessioned 2024-02-07T01:40:12Z -
dc.date.available 2024-02-07T01:40:12Z -
dc.date.created 2023-10-25 -
dc.date.issued 2023-07-12 -
dc.identifier.isbn 9781939133359 -
dc.identifier.uri http://hdl.handle.net/20.500.11750/47810 -
dc.description.abstract This paper investigates the feasibility of using inexpensive flash memory on new interconnect technologies such as CXL (Compute Express Link) to overcome the memory wall. We explore the design space of a CXL-enabled flash device and show that techniques such as caching and prefetching can help mitigate the concerns regarding flash memory’s performance and lifetime. We demonstrate using real-world application traces that these techniques enable the CXL device to have an estimated lifetime of at least 3.1 years and serve 68–91% of the memory requests under a microsecond. We analyze the limitations of existing techniques and suggest system-level changes to achieve a DRAM-level performance using flash. © 2023 by The USENIX Association All Rights Reserved. -
dc.language English -
dc.publisher USENIX Association -
dc.title Overcoming the Memory Wall with CXL-Enabled SSDs -
dc.type Conference Paper -
dc.identifier.scopusid 2-s2.0-85176948375 -
dc.identifier.bibliographicCitation USENIX Annual Technical Conference, pp.601 - 617 -
dc.identifier.url https://www.usenix.org/conference/atc23/presentation/yang-shao-peng -
dc.citation.conferencePlace US -
dc.citation.conferencePlace Boston -
dc.citation.endPage 617 -
dc.citation.startPage 601 -
dc.citation.title USENIX Annual Technical Conference -
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Department of Electrical Engineering and Computer Science Data-Intensive Computing Systems Laboratory 2. Conference Papers

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