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DBPS: Dynamic Block Size and Precision Scaling for Efficient DNN Training Supported by RISC-V ISA Extensions

Title
DBPS: Dynamic Block Size and Precision Scaling for Efficient DNN Training Supported by RISC-V ISA Extensions
Author(s)
Lee, SeunghyunChoi, JeikNoh, SeockhwanKoo, JahyunKung, Jaeha
Issued Date
2023-07-11
Citation
Design Automation Conference, pp.23709289
Type
Conference Paper
ISBN
9798350323481
ISSN
0738-100X
Abstract
Over the past decade, it has been found that deep neural networks (DNNs) perform better on visual perception and language understanding tasks as their size increases. However, this comes at the cost of high energy consumption and large memory requirement to train such large models. As the training DNNs necessitates a wide dynamic range in representing tensors, floating point formats are normally used. In this work, we utilize a block floating point (BFP) format that significantly reduces the size of tensors and the power consumption of arithmetic units. Unfortunately, prior work on BFP-based DNN training empirically selects the block size and the precision that maintain the training accuracy. To make the BFP-based training more feasible, we propose dynamic block size and precision scaling (DBPS) for highly efficient DNN training. We also present a hardware accelerator, called DBPS core, which supports the DBPS control by configuring arithmetic units with custom instructions extended in a RISC-V processor. As a result, the training time and energy consumption reduce by 67.1% and 72.0%, respectively, without hurting the training accuracy. © 2023 IEEE.
URI
http://hdl.handle.net/20.500.11750/47900
DOI
10.1109/DAC56929.2023.10248013
Publisher
ACM Special Interest Group on Design Automation (SIGDA), IEEE Council on Electronic Design Automation (CEDA)
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ETC 2. Conference Papers

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