High-Speed ADC Design for Wireline Receiver
- Title
- High-Speed ADC Design for Wireline Receiver
- Author(s)
- Seonho Gong
- DGIST Authors
- Seonho Gong ; Gain Kim ; Jonghyuk Yoon
- Advisor
- 김가인
- Co-Advisor(s)
- Jonghyuk Yoon
- Issued Date
- 2024
- Awarded Date
- 2024-02-01
- Type
- Thesis
- Description
- Hish speed ADC
- Table Of Contents
-
List of Contents
Abstract i
List of contents ii
List of tables · iii
List of figures vi
Ⅰ. Introduction
1.1 Background 1
1.2 Thesis Organization · 2
ⅠⅠ. Overview of SAR ADC
2.1 Operating Principle of SAR ADCs 3
2.2 ADC Performances Metrics · 4
2.3 Errors and Non-Ideal Effects in SAR ADCs 6
2.3.1 Quantization noise 6
2.3.2 kT/C Noise 6
2.3.3 Sampling jitter 7
2.4 Design Techniques for High-Speed SAR-Based ADCs · 8
2.4.1 Redundancy 8
2.4.2 Loop-Unrolling · 9
2.4.3 Two Alternating Comparators 11
2.4.4 Pipelined SAR 11
ⅠⅠⅠ. Proposed System
3.1 Design 13
3.2 Circuit Detail · 15
3.2.1 Bootstrapped switch 15
3.2.2 Dynamic Comparator · 17
3.2.3 CDAC structure 21
3.2.4 CDAC Reference Buffer 22
3.2.5 SAR-Logic · 23
3.3 Layout 27
IV. Simulation Result and Conclusion
4.1 Simulation Result 29
4.2 Conclusion · 32
- URI
-
http://hdl.handle.net/20.500.11750/48101
http://dgist.dcollection.net/common/orgView/200000725814
- Degree
- Master
- Publisher
- DGIST
- Related Researcher
-
-
Kim, Gain
- Research Interests Serial Link; OFDM; Discrete Multi-Tone; Wireline Transceiver; Communication Circuits
-
- Files in This Item:
-
There are no files associated with this item.
- Appears in Collections:
- Department of Electrical Engineering and Computer Science Theses Master
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