DGIST Scholar: A Highly Power-Efficient LDO with Reliable Low Input Voltage Operation

Title: A Highly Power-Efficient LDO with Reliable Low Input Voltage Operation

Citation: Woojin Jang. (2024). A Highly Power-Efficient LDO with Reliable Low Input Voltage Operation. doi: 10.22677/THESIS.200000723413

Description: low dropout regulator(LDO);self-oscillating charge pump(SOCP);NMOS pass transistor;highly power-efficient;low VIN operation

Table Of Contents: Ⅰ. Introduction 1
1.1 Background 1
1.1.1 Types of PMIC 1
1.1.2 Structure of power managing for battery-powered SoC 3

ⅠI. Literature Review 7
2.1 Conventional LDOs 7
2.1.1 Conventional ALDOs 7
2.1.2 Conventional DLDOs 8
2.2 ALDOs Targeted of Low Input Voltage 9
2.2.1 Time-based ALDOs 10
2.2.2 ALDOs with multi-stage EA 11
2.3 Pass Transistor under Low VDO conditions 12
2.3.1 Relationship between VDO and IL 13
2.3.2 Pass transistor selection 15
2.3.3 Limitation for lowering VDO in NMOS LDOs 16

ⅠII. Proposed System 19
3.1 System Design 19
3.1.1 Target specification of proposed LDO 19
3.1.2 Overall architecture of proposed LDO 20
3.2 Circuit Design 22
3.2.1 Self-oscillating charge pump(SOCP) 22
3.2.2 Delay cell 24
3.2.3 Invert phase-synchronized SOCP(I-SOCP) 25
3.2.4 Error amplifier(EA) 26
3.3 Stability Analysis 28

ⅠV. Measurement Results and Conclusions 35
4.1 Measurement Results 35

V. Conclusions and Future Works 47
5.1 Conclusions 47
5.2 Future Works 48

References 50

URI: http://hdl.handle.net/20.500.11750/48110
http://dgist.dcollection.net/common/orgView/200000723413

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