Fabrication of Domain Wall Inverter for Dynamic Logic Devices

Abstract

Recently, the spin torque majority gate (STMG) is paid great attention to developing next-generation logic devices with ultralow power consumptions since STMG can reduce the circuit architectures such as several transistors, circuit length, etc. Especially, the magnetic inverter is essential for the STMG logic devices to demonstrate NOT gate. There are several methods to realize NOT gate in the spintronics based on logic devices [1,2]. In this study, the interlayer exchange coupling (IEC) is used to demonstrate the STMG inverter based on the current-driven magnetic domain wall (DW) motion. In this research, we demonstrate the STMG inverter in the Ta/Pt/Co/Pt/Ru/Pt/Co Pt structure fabricated by the lift-off method including Chemical-Mechanical Planarization (CMP). The CMP Process is one of the wide-area planarization process operations, and here, matching the height of the passivated oxide layer and the bottom ferromagnetic layer. The top ferromagnetic layer is deposited on the bottom FM layer overlapped 3 mm region. Fig. 1 (a) shows the detailed procedure. Figure 1 (b) shows the structure of the STMG inverter. The stack consisted of an antiferromagnetic coupling of IEC using the perpendicularly magnetized Pt/Co/Pt/Ru/Pt/C /Pt structures. We will discuss processing the inverter. This result can open a new path to explore the next-generation logic devices based on the current-induced magnetic domain wall motion.