DGIST Scholar: Area-Efficient High-Speed ADCs For Wireline Data Communications

Citation: Eunki Song. (2024). Area-Efficient High-Speed ADCs For Wireline Data Communications. doi: 10.22677/THESIS.200000803503

Table Of Contents: Ⅰ. Introduction
1.1 Background 1
1.2 Thesis Organization 2
ⅠI. Overview of ADC
2.1 Operating Principle of SAR ADCs 3
2.2 ADC Performances Metrics 4
2.3 Errors and Non-Ideal Effects in SAR ADCs 6
2.3.1 Quantization noise 6
2.3.2 kT/C Noise 6
2.3.3 Sampling jitter 7
2.4 DAC for SAR ADCs 8
2.4.1 CDAC 8
2.4.2 Charge injection cell DAC 9
2.5 Methods for High-speed SAR ADCs 11
2.5.1 Two Alternating Comparators 11
2.5.2 Loop-Unrolled SAR ADC 11
2.5.4 Time interleaved ADC 13
ⅠII. Proposed System I
3.1 Design 15
3.3.1 Design 15
3.2 Modeling Detail 16
3.2.1 Proposed Ideas 16
3.2.2 Grouped SCIC-DAC based SAR ADCsc19
3.2.3 Implemented Modeling And Simulation Results 19
3.3 Conclusion 21
ⅠV. Proposed System II
4.1 Design 24
4.2 Circuit Detail 25
4.2.1 Proposed CICs 25
4.2.2 Monotonic CDAC 26
4.2.3 Memory Cell 27
4.2.4 CLK GEN 27
4.2.5 Switch 29
4.2.6 Comparator 30
4.2.7 Proposed Offset Calibration Cell 31
4.2.8 Layout Floor Plan 33
4.3 Simulation Results And Comparison 34
4.4 Conclusion 36

URI: http://hdl.handle.net/20.500.11750/57636
http://dgist.dcollection.net/common/orgView/200000803503

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