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Cooperative Memory Deduplication with Intel® Data Streaming Accelerator
Ji, Houxiang
;
Kim, Minho
;
Oh, Seonmu
;
Kim, Daehoon
;
Kim, Nam Sung
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Title
Cooperative Memory Deduplication with Intel® Data Streaming Accelerator
Issued Date
2025-01
Citation
Ji, Houxiang. (2025-01). Cooperative Memory Deduplication with Intel® Data Streaming Accelerator. IEEE Computer Architecture Letters, 24(1), 29–32. doi: 10.1109/LCA.2025.3527458
Type
Article
Author Keywords
Memory deduplication
;
hardware accelerator
;
operating system
ISSN
1556-6056
Abstract
Memory deduplication plays a critical role in reducing memory consumption and the total cost of ownership (TCO) in hyperscalers, particularly as the advent of large language models imposes unprecedented demands on memory resources. However, conventional CPU-based memory deduplication can interfere with co-running applications, significantly impacting the performance of time-sensitive workloads. Intel introduced the on-chip Data Streaming Accelerator (DSA), providing high-performance data movement and transformation capabilities, including comparison and checksum calculation, which are heavily utilized in the deduplication. In this work, we enhance a widely-used kernel-space memory deduplication feature, Kernel Samepage Merging (ksm ), by selectively offloading these operations to the DSA. Our evaluation demonstrates that CPU-based ksm can lead to 5.0-10.9× increase in the tail latency of co-running applications while DSA-based ksm limits the latency increase to just 1.6× while achieving comparable memory savings. © IEEE.
URI
http://hdl.handle.net/20.500.11750/57918
DOI
10.1109/LCA.2025.3527458
Publisher
Institute of Electrical and Electronics Engineers
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